{"title":"Design of a Low Power and High Speed Wallace Tree Encoder for Flash ADC","authors":"Shaik Rahil Hussain, Rajesh Kumar","doi":"10.2139/ssrn.3516639","DOIUrl":null,"url":null,"abstract":"An improved design of Wallace tree encoder is presented in this paper. Wallace tree encodes a thermometer code into binary code in a Flash ADC. It has the advantage of correcting bubble errors without the need of an extra bubble error correcting (BEC) block. It consists of full adder circuits and adds the number of 1’s generated through the comparator output in a Flash ADC. The new Wallace tree encoder is compared with the previously designed traditional Wallace tree encoder in 45nm technology. The results show that new design is efficient than the previous design. The proposed encoder dissipates 9.61μW power and has a delay of 29.5ps. The PDP and EDP is calculated to be 0.28 fJ and 0.83x10-26 Js.","PeriodicalId":11974,"journal":{"name":"EngRN: Engineering Design Process (Topic)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2020-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"EngRN: Engineering Design Process (Topic)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.2139/ssrn.3516639","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
An improved design of Wallace tree encoder is presented in this paper. Wallace tree encodes a thermometer code into binary code in a Flash ADC. It has the advantage of correcting bubble errors without the need of an extra bubble error correcting (BEC) block. It consists of full adder circuits and adds the number of 1’s generated through the comparator output in a Flash ADC. The new Wallace tree encoder is compared with the previously designed traditional Wallace tree encoder in 45nm technology. The results show that new design is efficient than the previous design. The proposed encoder dissipates 9.61μW power and has a delay of 29.5ps. The PDP and EDP is calculated to be 0.28 fJ and 0.83x10-26 Js.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
