Design techniques for a PAL/NTSC mixed-signal video encoder with 66 dB SNR and 0.4% differential gain

Abstract

This paper describes the integration of ASIC and Mixed Signal design and simulation techniques in the design of a Mixed-Signal Digital Video Encoder chip which produces an analog output video signal. The result was fast time to market together with studio quality analog video output performance-66 dB typ SNR, 0.4% Differential Gain and 0.2/spl deg/ Differential Phase. A fully-automated design flow was used for the entire logic functionality of the chip in order to meet time-to-market requirements. Low die cost (compatible with hand-craft techniques) was achieved by aggressive use of CAD tools, process technology, and filter design techniques. Full functionality on first silicon was achieved by use of standard cell DACs, pads, Amplifier, and Band-Gap reference, and the use of a simulation test-bench which allowed frames of video to be simulated by the chip model, and the resultant simulation output to be captured and viewed on a video monitor. Some of the practical aspects of timing analysis and dynamic power estimation are also described.