Influence of substrate-induced thermal stress on the superconducting properties of V 3 Si thin films

Abstract

Thin films of superconducting V$_3$Si were prepared by means of RF sputtering from a compound V$_3$Si target at room temperature onto sapphire and oxide-coated silicon wafers, followed by rapid thermal processing under secondary vacuum. The superconducting properties of the films thus produced are found to improve with annealing temperature, which is ascribed to a reduction of defects in the polycrystalline layer. Critical temperatures ($T_\text{c}$) up to $15.3\,$K were demonstrated after thermal processing, compared to less than $1\,$K after deposition. The $T_\text{c}$ was found to always be lower on the silicon wafers, by on average $1.9(3)\,$K for the annealed samples. This difference, as well as a broadening of the superconducting transitions, is nearly independent of the annealing conditions. In-situ XRD measurements reveal that the silicide layer becomes strained upon heating due to a mismatch between the thermal expansion of the substrate and that of V$_3$Si. Taking into account the volume reduction due to crystallization, this mismatch is initially larger on sapphire, though stress relaxation allows the silicide layer to be in a relatively unstrained state after cooling. On oxidized silicon however, no clear evidence of relaxation upon cooling is observed, and the V$_3$Si ends up with an out-of-plane strain of 0.3\% at room temperature. This strain increases as the sample is cooled down to cryogenic temperatures, though the deformation of the polycrystalline layer is expected to be highly inhomogeneous. Taking into account also the reported occurrence of a Martensitic transition just above the critical temperature, this extrapolated strain distribution is found to closely match an existing model of the strain dependence of A-15 superconducting compounds.