A 10b 42MS/s SAR ADC with Power Efficient Design

Abstract

A 10b 42MS/s power-efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) is presented in this paper. The ADC structure is optimized for lower power consumption. For this purpose, an accuracy-enhanced DAC switching method and a comparator that can dynamically adjust current to save energy are introduced. The linearity of SAR ADCs can be improved without adding capacitors or calibration logic in this way. In 130nm CMOS process, simulation results show the ADC achieves a SNDR of 60dB for Nyquist input and consumes $510 \mu \mathrm{W}$ under a 1.2V power supply.