A GALS Router for Asynchronous Network-on-Chip

Abstract

A scalable asynchronous NoC router with lower power consumption and latency comparing to a synchronous design is introduced in this article. It employs GALS interfaces (synchronous to asynchronous/asynchronous to synchronous), imposing negligible area overhead to handle the Metastability issue. It is synthesized with the help of Persia tool, resulting in 23165 transistors. The power consumption and delay factor have been evaluated by means of H-Spice toolset in 90nm manufacturing technology. According to the experimental results the proposed asynchronous design consumes less power than synchronous scheme by removing clock signals. The imposed area overhead of asynchronous design is reported 36% higher than synchronous one.