A novel high-performance predictable circuit architecture for the deep sub-micron era

Abstract

Current VLSI design techniques focus on four major goals: higher integration, faster speed, lower power, and shorter time-to-market. Those goals have been accomplished mainly by deep sub-micron technology along with voltage scaling. However, scaling down feature size causes larger interwire capacitance which is responsible for large crosstalk between concerned interconnects. We are currently facing signal integrity problems never experienced before, such that accurate function predictability of circuits under certain input conditions may be questionable, not to mention performance and power dissipation predictability. In this paper we suggest a novel predictable circuit architecture, named optimized overlaying array based architecture (O/sup 2/ABA), especially suited for the deep sub-micron regime. O/sup 2/ABA achieves reduction of crosstalk by considering the current directions and by reducing interwire capacitance. The introduction of unit cell leads to high regularity, which makes the performance predictable even before layout, and shortens time-to-design. O/sup 2/ABA is compared with other design styles, such as custom design, PLA and Weinberger array, to show its advantages.