Challenges in CMOS imager design

Abstract

Summary form only given. In the last decade, active pixel sensors (APS), which are fabricated in a commonly used CMOS process, enabled the design of image sensors with integrated "intelligence". Current state of the art CMOS imagers allow integration of all functions required for timing, exposure control, color processing, image enhancement, image compression and ADC on the same die. Moreover, systems with wide dynamic range, motion detection and non-standard readout can be designed. CMOS imagers also offer significant advantages in terms of low-power, low-voltage and monolithic integration, rivaling traditional charge coupled devices (CCD). This paper covers state of the art CMOS imager systems and design challenges with the advanced CMOS technologies available. Specifically, ways to improve power consumption in such "smart" sensors, required to cope with the current demand for portable systems are reviewed. In addition, pixel optimization is revisited as more advanced processes are used and pixel pitch is reduced.