JFET Region Design Trade-Offs of 650 V 4H-SiC Planar Power MOSFETs

Abstract

650 V silicon carbide (SiC) power MOSFETs with various JFET region design have been successfully fabricated on 6-inch wafers in a state-of-the-art commercial SiC foundry. The trade-offs between the performance and reliability of the 650 V MOSFETs are studied. In particular, the impact of the JFET region design on the reliability of the SiC MOSFETs and ON-resistance is studied through TCAD simulations and device characterizations. Simulations show that narrower JFET width lowers the electric field at the center of the JFET region and can potentially mitigate device failures under high-temperature reverse bias (HTRB) test with a penalty of higher ON-resistance. It is experimentally demonstrated with the fabricated MOSFETs that the ON-resistance can be reduced with higher JFET region doping and tighter layout design. Compared with recently published studies on 600 V class SiC power MOSFETs, we report the lowest specific ON- resistance (R_on,sp) of 2.06 mΩ · cm² (further reducible through tighter layout design) while having a narrow JFET region for device reliability.