Solid State Electronics Letters最新文献

An off-chip capacitor-free low-dropout (LDO) regulator using an improved frequency compensation scheme is proposed. The proposed LDO regulator employs a class-AB error amplifier and a load-current tracker. Outstanding line regulation, load regulation and transient response are achieved. SPICE simulation based on SMIC 0.35 µm CMOS technology shows that the proposed LDO regulator has a low frequency gain over 100 dB and a unity-gain bandwidth in the MHz range. In terms of transient response, the 1% settling time is shorter than 0.2 µs.

Multi-finger gate structure has been extensively applied to layout MOS transistors in RF analog circuits. The main advantage of this method is that a large drain current can be obtained with a compact silicon area. Furthermore, because of the reduced gate resistance, the cut-off frequency obtained from the multi-finger layout MOS transistor is higher than that of a single-finger transistor. This work will provide an empirical study on the impact of multi-finger layout on cut-off frequency for nanometer MOS transistors. It is shown that increasing the number of fingers in multi-finger layout has diminishing returns, and there exists an optimal number of fingers to achieve the highest cut-off frequency, and hence the RF performance of the transistor.

A multi-level DAC with high intrinsic linearity and low power consumption enables a greater design space for wide-band continuous-time (CT) Delta-Sigma modulators (DSMs). This manuscript introduces an intrinsically highly linear 5-level switched-capacitor (SC) DAC with a power-saving charge recycling technique for wideband CT DSMs. We also adopt a distinct modulator architecture that places a large low-pass filter (LPF) capacitor at the input of the first amplifier. This architecture substantially enhances the modulator’s power efficiency and restores the modulator’s alias rejection ratio (AR) in the presence of an SC type of DAC. To validate the proposed techniques, a DSM prototype with a 10-MHz bandwidth and 800 MHz sampling rate ($f_s$) is fabricated in a 65-nm CMOS technology. Consuming 1.3 mW from a 1.2-V supply, the prototype achieves a peak signal-to-noise-plus-distortion ratio of 72.3 dB and a dynamic range of 73.3 dB in experiments. The corresponding Warden’s and Schreier’s figures of merits are 19.3 fJ/conv-step and 171.2 dB, respectively. The measured ARs are 52.7 dB and 54.3 dB at $f_s$ and $2f_s$, respectively. The DSM further tolerates an rms clock jitter of 11 ps.

The convex corner compensation methodes to manufacture diaphragms with V-grooves of semiconductor pressure sensors have been widely introduced. However, these methods do not seem to be efficiently used to manufacture very thin diaphragms with square masses. In order to make thin silicon diaphragms with different thicknesses where stresses are compensated, the convex corner compensation method to preserve square shaped convex corners should be established. In this paper, we have designed convex corner compensation patterns to make diaphragms of V-groove structures with mass and proved the superiority of this method by reasonable analysis.

A novel classification technique is applied for identifying carbon nanotube FET and quantum wire FET based on their electrical characteristics and percentage error is estimated using multi-layer perceptron analysis to justify the accuracy of computation. Two different cross-validation methods, namely decision table and multilayer perceptron (MLP) are applied on same data set of both the devices, and results speak about higher accuracy when MLP is performed. Also, for different testing-training set of data, MLP performs far better than conventional decision table approach; when correlation coefficient, mean absolute error, root mean squared error, relative absolute error and root relative squared error are computed. For comparative study, similar geometrical configuration, and equivalent biasing arrangement of both the devices are assumed, and identical number of iterations is performed for equal subsets. Results speak supremacy of MLP technique applied for classification and identification of nanometric devices based on their electronic attributes.

A low power current comparison based voltage detector with on-chip detection voltage trimming is proposed in this paper. The proposed trimming technique achieves both detection voltage trimming and detection voltage accuracy trimming. The performance of the proposed circuit is validated by simulation using a 0.5 $\mu$m CMOS process. A short power-on rising time ($t_{rise}$) of less than 1 ms can be achieved due to the utilization of current comparison technique. Trimming accuracy on the detection voltage at $\pm$1.875% is obtained. The proposed circuit consumes 140 $\mu$W at supply voltage of 5 V. The overall active silicon area of the proposed circuit is 27900 $\mu$${\text{m}}^2$, which is comparable with that of other reported circuits without trimming functions. The proposed circuit is suitable for the application in a variety of power management application where energy efficiency is a consideration.