A Data Eye Width Improved and ODT PVT Tolerance Enhanced DDR4 SDRAM Using Fast Clock Gating and tADC Self-align

Abstract

An 8Gb3200Mbps DDR4 SDRAM with fast clock gating and ODT path self-align technique is presented. Fast clock gating is utilized in the DDR4 SDRAM to pursue cut down DLL, read, write and ODT Paths stage, thus data jitters and current consumption can be reduced. ODT path delay self-align method is proposed to the DDR4 SDRAM which is implemented in DRAM process. Measurement results show fast clock gating can reduce 12 stages in DLL, read, write and ODT path and reduce 600uA current, and 5.4% jitters in Read and ODT path. What’s more, the measurement results also show the tADC variation is reduced from 220ps to 30ps with delay self-align technique.