9T balanced SRAM cell for low power operation

Abstract

The increasing market of mobile devices and battery powered portable electronic systems is creating demands for chips that consume the smallest possible amount of power. Static random access memories (SRAMs) consist of almost 90% of very large scale integrated (VLSI) circuits. The power consumption and speed of SRAMs are important issue that has lead to multiple designs with the purpose of minimizing the power consumption during both read and write operations. In this paper, we have proposed a new SRAM cell architecture which consists of an asymmetric inverter pair to reduce the power consumption. The proposed circuit consumes lower power during read and write operations compared to 6T conventional circuit. The main disadvantage of the proposed cell is its larger area occupation. The stability and speed of the cell are deteriorated which can be improved by proper sizing of the tail transistor.