Subutai: Distributed Synchronization Primitives in NoC Interfaces for Legacy Parallel-Applications

2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC) Pub Date : 2018-06-01 DOI:10.1145/3195970.3196124

R. Cataldo, Ramon Fernandes, Kevin J. M. Martin, Martha Johanna Sepúlveda, A. Susin, C. Marcon, J. Diguet

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引用次数: 5

Abstract

Parallel applications are essential for efficiently using the computational power of a Multiprocessor System-on-Chip (MPSoC). Unfortunately, these applications do not scale effortlessly with the number of cores because of synchronization operations that take away valuable computational time and restrict the parallelization gains. Moreover, synchronization is also a bottleneck due to sequential access to shared memory. We address this issue and introduce ”Subutai”, a hardware/software (HW/SW) architecture designed to distribute essential synchronization mechanisms over the Network-on-Chip (NoC). It includes Network Interfaces (NIs), drivers and a custom library of a NoC-based MPSoC architecture that speeds up the essential synchronization primitives of any legacy parallel application. Besides, we provide a fast simulation tool for parallel applications and a HW architecture of the NI. Experimental results with PARSEC benchmark show an average application speedup of 2.05 compared to the same architecture running legacy SW solutions for 36% overhead of HW architecture.

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遗留并行应用程序的NoC接口中的分布式同步原语

并行应用对于有效利用多处理器单片系统(MPSoC)的计算能力至关重要。不幸的是，由于同步操作占用了宝贵的计算时间并限制了并行化的收益，因此这些应用程序并不能随着内核数量的增加而轻松扩展。此外，由于对共享内存的顺序访问，同步也是一个瓶颈。我们解决了这个问题，并引入了“Subutai”，这是一种硬件/软件(HW/SW)架构，旨在通过片上网络(NoC)分发基本同步机制。它包括网络接口(NIs)，驱动程序和基于noc的MPSoC架构的自定义库，可以加速任何遗留并行应用程序的基本同步原语。此外，我们还提供了一个并行应用的快速仿真工具和NI的硬件架构。PARSEC基准测试的实验结果显示，与运行遗留软件解决方案的相同架构相比，应用程序的平均加速速度为2.05，而硬件架构的开销为36%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

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