{"title":"A low complexity joint equalizer and decoder for 1000Base-T Gigabit Ethernet","authors":"E. Haratsch, K. Azadet","doi":"10.1109/CICC.2000.852709","DOIUrl":null,"url":null,"abstract":"A VLSI architecture for low complexity joint decoding and equalization for 1000Base-T Gigabit Ethernet is presented. A one-tap parallel decision-feedback decoder jointly decodes the trellis and cancels the ISI due to the first tap of the post-cursor channel impulse response. The one-dimensional branch metrics are precomputed in a look-ahead fashion to meet the speed requirements. The less significant tail of the channel impulse response is canceled with a simple decision-feedback prefilter. The design has been implemented in 3.3 V, 0.25 /spl mu/m standard cell CMOS process for operation at 125 MHz.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"35 1","pages":"465-468"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2000.852709","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
A VLSI architecture for low complexity joint decoding and equalization for 1000Base-T Gigabit Ethernet is presented. A one-tap parallel decision-feedback decoder jointly decodes the trellis and cancels the ISI due to the first tap of the post-cursor channel impulse response. The one-dimensional branch metrics are precomputed in a look-ahead fashion to meet the speed requirements. The less significant tail of the channel impulse response is canceled with a simple decision-feedback prefilter. The design has been implemented in 3.3 V, 0.25 /spl mu/m standard cell CMOS process for operation at 125 MHz.
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