Zhiqiang Wang, Xin Liu, Zhiqiang Li, Xiaosong Wang, Minghua Wang, Quan Li, Yan Li, Yu Liu
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引用次数: 0
Abstract
This paper presents a four-way current-combining Ka-band power amplifier(PA) in 65-nm CMOS technology. A symmetrical, transmission line based four-way current combiner, together with output transformers, is used to transfer the high load impedance(4* 𝑍 𝐿 ) to the desired 𝑍 𝑜𝑝𝑡 foreachpowerunitcell.Besides,bothinterstage/inputflexible matching transformers and the power splitter are optimized to improve the performance. Based on the methodology mentioned above, the power amplifier demonstrates a small-signal gain of about 24.12 dB, a saturated output power of 21.56 dBm, and a peak power-added efficiency of 27.3% at 35GHz.
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