{"title":"An open-loop fractional divider based on direct phase synthesis","authors":"Pao-Lung Chen","doi":"10.1109/ICCE-TW.2016.7521069","DOIUrl":null,"url":null,"abstract":"This work presents an open-loop fractional divider based on direct phase synthesis. The proposed fractional divider is pure digital circuit and with low cost. It also has fast switching speed within 2 clock cycles. The fractional part can range from 2-1 ~ 2-24 with fine resolution. An example by using FPGA of proposed fractional frequency divider has been successfully developed.","PeriodicalId":6620,"journal":{"name":"2016 IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW)","volume":"26 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCE-TW.2016.7521069","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This work presents an open-loop fractional divider based on direct phase synthesis. The proposed fractional divider is pure digital circuit and with low cost. It also has fast switching speed within 2 clock cycles. The fractional part can range from 2-1 ~ 2-24 with fine resolution. An example by using FPGA of proposed fractional frequency divider has been successfully developed.