Silicon Heterostructures as High Performance Field Effect Transistor

Abstract

The advances in Silicon technology have driven the MOSFET device fabrication towards submicron regime. Despite all these advances in technology special effects come into play such as velocity overshoot, short channel effects and Drain Induced Barrier Lowering (DIBL). For MOSFET with large geometry, they experience a number of effects ranging from low clock frequencies due to high input capacitance, high threshold voltage hence high power consumption and lower trans-conductance. As the dimensions are scaled down, the drain current increases, evidence that sub-micron devices have better performance as compared to un-scaled devices. It can also be noted that there is a strong correlation between device dimensions and device performance. Also from transfer curves the output drain current decreases with increase in the drain voltage but it was further established from the transfer curves that the trans-conductance of the device increases with scaling at a constant voltage. This shows that sub-micron device has better performance as compared to unscaled device.