{"title":"A novel combined first and second order Lagrange interpolation sampling process for a digital class D amplifier","authors":"V. Adrian, B. Gwee, J. Chang","doi":"10.1109/ISCAS.2004.1328726","DOIUrl":null,"url":null,"abstract":"In this paper, we propose a sampling process for low voltage (1.1V) power-critical low-distortion digital class D amplifiers. The sampling process combines first and second-order Lagrange interpolation techniques to effectively increase the sampling rate without the usual overheads. The computation is also simple. The complete class D amplifier features a very low power dissipation (58.8/spl mu/W), low total harmonic distortion (-85.6dB FS) and high signal-to-noise ratio (99dB FS). The power saving is /spl sim/21% and the THD is improved by 9.8dB FS compared to a design embodying only a first order sampling process. We also provide an analysis of the power dissipation of the load power.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"2007 1","pages":"III-233"},"PeriodicalIF":0.0000,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS.2004.1328726","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
In this paper, we propose a sampling process for low voltage (1.1V) power-critical low-distortion digital class D amplifiers. The sampling process combines first and second-order Lagrange interpolation techniques to effectively increase the sampling rate without the usual overheads. The computation is also simple. The complete class D amplifier features a very low power dissipation (58.8/spl mu/W), low total harmonic distortion (-85.6dB FS) and high signal-to-noise ratio (99dB FS). The power saving is /spl sim/21% and the THD is improved by 9.8dB FS compared to a design embodying only a first order sampling process. We also provide an analysis of the power dissipation of the load power.
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