{"title":"Recycled integrated circuit detection using reliability analysis and machine learning algorithms","authors":"Udaya Shankar Santhana Krishnan, Kalpana Palanisamy","doi":"10.1049/cdt2.12005","DOIUrl":null,"url":null,"abstract":"<p>The use of counterfeit integrated circuits (ICs) in electronic products decreases its quality and lifetime. Recycled ICs can be detected by the method of aging analysis. Aging is carried out through reliability analysis with the effect of hot carrier injection and bias temperature instability (BTI). In this work, three machine learning methods, namely K-means clustering, back propagation neural network (BPNN) and support vector machines (SVMs), are used to detect the recycled IC aged for a shorter period (1 day) with minimum data size. This work also distinguishes the effects of degradation due to process variations and reliability effects. The reliability and Monte Carlo simulation are performed on benchmark circuits such as c17, s27, b02 and fully differential folded-cascode amplifier using the Cadence Virtuoso tool, and the parameters such as minimum voltage, delay value, supply current, gain, phase margin and bandwidth are measured. Machine learning methods are developed using MATLAB to train and classify the parameters. From the results obtained, it is observed that the classification rate for the benchmark circuits is 100%, and using BPNN, K-means clustering and SVM and the proposed method, recycled IC or used IC is detected even if it was used for 1 day.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"15 1","pages":"20-35"},"PeriodicalIF":1.1000,"publicationDate":"2020-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12005","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IET Computers and Digital Techniques","FirstCategoryId":"94","ListUrlMain":"https://onlinelibrary.wiley.com/doi/10.1049/cdt2.12005","RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 2
Abstract
The use of counterfeit integrated circuits (ICs) in electronic products decreases its quality and lifetime. Recycled ICs can be detected by the method of aging analysis. Aging is carried out through reliability analysis with the effect of hot carrier injection and bias temperature instability (BTI). In this work, three machine learning methods, namely K-means clustering, back propagation neural network (BPNN) and support vector machines (SVMs), are used to detect the recycled IC aged for a shorter period (1 day) with minimum data size. This work also distinguishes the effects of degradation due to process variations and reliability effects. The reliability and Monte Carlo simulation are performed on benchmark circuits such as c17, s27, b02 and fully differential folded-cascode amplifier using the Cadence Virtuoso tool, and the parameters such as minimum voltage, delay value, supply current, gain, phase margin and bandwidth are measured. Machine learning methods are developed using MATLAB to train and classify the parameters. From the results obtained, it is observed that the classification rate for the benchmark circuits is 100%, and using BPNN, K-means clustering and SVM and the proposed method, recycled IC or used IC is detected even if it was used for 1 day.
期刊介绍:
IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test.
The key subject areas of interest are:
Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation.
Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance.
Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues.
Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware.
Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting.
Case Studies: emerging applications, applications in industrial designs, and design frameworks.