Jia Liu, Yusen Qin, T. Li, Yuxin Wang, Weidong Yang, Jun Liu, Ruzhang Li
{"title":"Using VerilogA for modeling of Single Event current pulse: Implementation and application","authors":"Jia Liu, Yusen Qin, T. Li, Yuxin Wang, Weidong Yang, Jun Liu, Ruzhang Li","doi":"10.1109/CSTIC.2017.7919830","DOIUrl":null,"url":null,"abstract":"In the sub-100nm bulk CMOS process technologies, the Single Event Effect (SEE) becomes one of the most critical reliability issues in the semiconductor devices and ICs that are used for the space applications. The modeling of Single Event (SE) current pulse is very important and challenging. In this paper we give the 3D TCAD simulation results of the SE current pulse (SECP) in the devices, and develop a compact model using VerilogA (VA) behavioral language. This model could be used for the validation of the Radiation-Hardened (RH) approaches in the circuit-level simulations.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"115 1","pages":"1-3"},"PeriodicalIF":0.0000,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 China Semiconductor Technology International Conference (CSTIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSTIC.2017.7919830","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In the sub-100nm bulk CMOS process technologies, the Single Event Effect (SEE) becomes one of the most critical reliability issues in the semiconductor devices and ICs that are used for the space applications. The modeling of Single Event (SE) current pulse is very important and challenging. In this paper we give the 3D TCAD simulation results of the SE current pulse (SECP) in the devices, and develop a compact model using VerilogA (VA) behavioral language. This model could be used for the validation of the Radiation-Hardened (RH) approaches in the circuit-level simulations.