N. Vamsi, Sesha Sairam Ragulagadda, A. Dutta, S. Singh
{"title":"A −34dBm sensitivity battery-less wake-up receiver with digital decoder","authors":"N. Vamsi, Sesha Sairam Ragulagadda, A. Dutta, S. Singh","doi":"10.1109/APCCAS.2016.7804076","DOIUrl":null,"url":null,"abstract":"A new approach for a battery-less 915MHz ISM band wake-up receiver with digital decoder for wireless sensor network is designed and presented. The proposed receiver architecture is based on a differential rectifier with gate-driver circuit using an ON-OFF Keying modulation for the input signal. To enhance the power conversion efficiency (PCE) of the rectifier for the low input power level, appropriate gate-drive voltages for each stage of the rectifier are generated using a chain of auxiliary floating rectifier cells. The wake-up receiver is designed in 0.18μm CMOS technology and achieves a sensitivity of −34 dBm at 0.8V for a 100 kbps.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS.2016.7804076","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A new approach for a battery-less 915MHz ISM band wake-up receiver with digital decoder for wireless sensor network is designed and presented. The proposed receiver architecture is based on a differential rectifier with gate-driver circuit using an ON-OFF Keying modulation for the input signal. To enhance the power conversion efficiency (PCE) of the rectifier for the low input power level, appropriate gate-drive voltages for each stage of the rectifier are generated using a chain of auxiliary floating rectifier cells. The wake-up receiver is designed in 0.18μm CMOS technology and achieves a sensitivity of −34 dBm at 0.8V for a 100 kbps.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
