X. Qi, Gaofeng Wang, Zhiping Yu, R. Dutton, T. Young, N. Chang
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引用次数: 65
Abstract
On-chip inductance modeling of VLSI interconnects is presented which captures 3D geometry from layout design and process technology information. Analytical formulae are derived for quick and accurate inductance estimation which can be used in circuit simulations and whole chip extraction screening process. Circuit simulations show critical global wire inductive effects as well as power and ground inductive noise.
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