Pixel-based pipeline hardware architecture for high-performance Haar-like feature extraction

Y. Fujita, F. An, A. Luo, X. Zhang, Lei Chen, H. Mattausch
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Abstract

Feature extraction, which is one of the basic tasks for pattern recognition, has often high computational cost and large memory usage. In this work, we propose a pixel-based pipeline hardware architecture for Haar-like feature extraction, implemented in 0.18 μm CMOS technology with 1.76 mm2 core area. Pixel-input speed relies on the working frequency of the image sensor so that features are extracted in real time without on-chip image buffer and complex computational procedures. The fabricated chip consumes 4.78 mW power at 1.8 V supply voltage and 12.5 MHz frequency during 30 fps VGA video input. Furthermore, a processing time of 3.07 ms per VGA frame with power dissipation of 36.25 mW at 100 MHz frequency is possible.
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基于像素的流水线硬件架构,用于高性能haar类特征提取
特征提取是模式识别的基本任务之一,计算量大,内存占用大。在这项工作中,我们提出了一种基于像素的流水线硬件架构,用于haar类特征提取,该架构采用0.18 μm CMOS技术,核心面积为1.76 mm2。像素输入速度依赖于图像传感器的工作频率,因此无需片上图像缓冲和复杂的计算过程即可实时提取特征。该芯片在1.8 V电源电压和12.5 MHz频率下,在30 fps的VGA视频输入下,功耗为4.78 mW。此外,在100 MHz频率下,每个VGA帧的处理时间为3.07 ms,功耗为36.25 mW是可能的。
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