Coral-automating the design of systems-on-chip using cores

Abstract

The reuse of pre-designed and pre-verified IP blocks or cores has been touted as the enabler of large systems-on-chip designs. However, the lack of appropriate tools and the increasing complexity of such cores makes them inherently difficult and error-prone to use. This paper presents a new tool, "Coral", for the design of systems using cores. Coral is based on a new synthesizable virtual design representation which is automatically synthesized to a real design. Novel algorithms are presented to interconnect cores automatically as well as configure system parameters, such as interrupt maps, DMA channel assignments, etc. Coral significantly reduces the time, complexity and potential for errors associated with SoC integration.