Fast high-level fault simulator

Q3 Arts and Humanities Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI:10.1109/ICECS.2004.1399748
S. Deniziak, K. Sapiecha
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引用次数: 5

Abstract

A new fast fault simulation technique is presented for calculating fault propagation through high level primitives (HLPs). Reduced ordered ternary decision diagrams are used to describe HLPs. The technique is implemented in an HTDD fault simulator. The simulator is evaluated with some ITC99 benchmarks. Besides high efficiency (in comparison with existing fault simulators), it shows flexibility for the adoption of a wide range of fault models.
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快速高级故障模拟器
提出了一种利用高级原语计算故障传播的快速故障仿真技术。简化有序三元决策图用于描述hlp。该技术在HTDD故障模拟器中实现。模拟器用一些ITC99基准测试进行了评估。除了效率高(与现有故障模拟器相比)外,它还具有采用多种故障模型的灵活性。
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来源期刊
Giornale di Storia Costituzionale
Giornale di Storia Costituzionale Arts and Humanities-History
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