Laser spike annealing and SiGe dummy pattern layout study to improve contact misalignment overlay issue

Abstract

The use of strained SiGe is essential to improve PFET MOS device performance. However, the structure is susceptible to strain relaxation and wafer deformation during thermal annealing. The accumulation of stress in the wafer needs to be controlled to minimize contact misalignment overlay issue. This paper analyzes laser spike annealing impact and SiGe dummy pattern layout impact on contact overlay by experiments on 28n m technology, design guide lines on shape of dummy SiGe patterns for slip free condition have been investigated and clarified. With optimized dummy SiGe patterns and laser spike annealing, random component of contact misalignment has been successfully reduced to normal level.