A system-on-chip for series arc fault acquisition in smart grid based on two configurable sampling rate SAR ADCs

Abstract

Arc faults in power systems may cause significant damage to equipment and even lead to electrical fires and hazard for personnel if they are not detected and isolated promptly. The series arc fault in a distribution system can be more dangerous compared to the parallel arc fault, because its low fault current will hinder the circuit breakers from responding in a timely manner. Therefore, it is necessary to properly detect the series arc fault. In this paper, a system-on-chip (SoC) for series AC arc fault acquisition is presented, which is based on two channels of configurable sampling rate successive approximation register (SAR) analog-to-digital-converters (ADCs). As the arc faults with different loads have different characteristics and may need a higher sampling rate under some circumstances, the adjustable sampling rate can meet varying needs. The system is implemented using a 55 nm CMOS process with a die area of 4.683 mm 2 and power dissipation of 75.9 mW. The proposed SAR ADC design can achieve a good Schreier figure-of-merit (FoM) of 161 dB at 1 MS/s sampling rate. With this ADC design, the SoC can complete arc faults acquisition with high precision and configurable sampling rate at a low cost. Meanwhile, the system can sample voltage and current signals from the smart grid respectively to initially locate the arc fault. words: