A 5.4-mW 4-Gb/s 5-band QPSK transceiver for frequency-division multiplexing memory interface

Wei-Han Cho, Yilei Li, Yanghyo Kim, Po-Tsang Huang, Yuan Du, S. Lee, Mau-Chung Frank Chang
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引用次数: 26

Abstract

This paper presents a novel self-equalized and skewless frequency-division multiplexing memory interface. To prove its feasibility, we have realized a 5-band QPSK transceiver in 40 nm CMOS to transmit up to 4 Gb/s through 10 orthogonal communication channels (each with 400 Mb/s) via on-chip TSV emulator with effective loading of 1 pF or 5-cm FR-4 PCB trace. With differential current-mode signaling, the transceiver consumes only 5.4 mW and takes only 80×100 μm2. A real-time flexible BER testing platform is established to prove that the BER of the transceiver is less than 1012.
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一种5.4 mw 4gb /s 5波段QPSK收发器,用于频分复用存储接口
提出了一种新的自均衡无偏频分复用存储接口。为了证明其可行性,我们在40 nm CMOS中实现了一个5波段QPSK收发器,通过片上TSV仿真器通过10个正交通信通道(每个通道400 Mb/s)传输高达4 Gb/s,有效负载为1 pF或5 cm FR-4 PCB走线。采用差分电流模式信号,收发器功耗仅为5.4 mW,占用面积仅为80×100 μm2。建立了实时灵活误码率测试平台,验证了收发器的误码率小于1012。
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