Graphene nanoribbon based static random access memory for better noise margin and power reduction

Abstract

In the post silicon era as the silicon reaches its fundamental scaling limits graphene nanoribbons is expected to take over and thus continue the Moore's law about the diminishing size of transistors. Graphene nanoribbons facilitates high speed low power switching applications. Low and high field mobilities of the graphene nanoribbons are found to be higher than the CNTs and CMOS keeping the same unit cell. Such properties of graphene nanoribbons are used in the paper to define RAM memory using GNRs as an effective substitute to CMOS and CNTFETs cache memory. Graphene nanoribbon crossbars are used as the basic programmable devices. This 2-D arrangement of GNRs creates programmable diodes at intersection of each horizontal and vertical GNR rod thus opening up new avenues for building high speed memory and digital devices. The graphene nanoribbons based memory is better than the SRAM in terms of speed, density and performance metrics as well. The noise margin of GNR based memory will be .2 volts higher with respect to lower and upper limits than CMOS counterpart used presently as demonstrated by simulations in the paper. GNR based memory would be operating in the 10 nanometres scale and would be 25-50 per cent denser than the existing SRAM.