A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference

Min-Shueh Yuan, Chao-Chieh Li, Chia-Chun Liao, Yu-Tso Lin, Chih-Hsien Chang, R. Staszewski
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引用次数: 4

Abstract

The current paradigm of frequency synthesis for short-range wireless transceivers, such as BLE, is to use a crystal oscillator (XO) in the tens-of-MHz range as a frequency reference (FREF) to phase lock an RF oscillator [1-4]. This ensures a sufficiently wide PLL bandwidth of tens to hundreds of kHz to quickly acquire a new channel and to suppress lower-frequency phase noise (PN) of the RF oscillator. The latter requirement can be alleviated by substantially lowering the flicker PN of a digitally controlled oscillator (DCO) thus allowing to freeze its tuning word updates during receive (RX) packets and further directly FM-modulating the DCO during transmit (TX) packets [1]. However, an all-digital PLL (ADPLL) is still needed just to quickly settle the DCO to each new channel.
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一个在16nm FinFET中的0.45V亚毫瓦全数字锁相环,用于蓝牙低功耗(BLE)调制和使用32.768kHz参考的瞬时信道跳变
目前用于短距离无线收发器(如BLE)的频率合成范例是使用几十mhz范围内的晶体振荡器(XO)作为频率基准(FREF)来锁相RF振荡器[1-4]。这确保了数十至数百kHz的足够宽的锁相环带宽,以快速获取新通道并抑制射频振荡器的低频相位噪声(PN)。后一种要求可以通过大幅降低数字控制振荡器(DCO)的闪烁PN来缓解,从而允许在接收(RX)数据包期间冻结其调谐字更新,并在发送(TX)数据包期间进一步直接fm调制DCO[1]。然而,为了快速解决每个新通道的DCO,仍然需要全数字锁相环(ADPLL)。
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