I. Subbiah, Andreas Suss, A. Kravchenko, B. Hosticka, W. Krautschneider
{"title":"A low-noise saturation-stacked bandgap reference for image sensor applications","authors":"I. Subbiah, Andreas Suss, A. Kravchenko, B. Hosticka, W. Krautschneider","doi":"10.1109/SMICND.2014.6966450","DOIUrl":null,"url":null,"abstract":"A novel architecture for a bandgap voltage reference is presented in this paper. The voltage reference, designed for image sensor applications, is primarily targeted for a low-noise operation along with other practical constraints such as high power supply rejection, temperature immunity and short start-up time. The analysis and operation of the circuit is discussed and the trade-offs involved in the implementation aspects are examined. The measurement results of the fabricated circuit in a 0.35-μm CMOS process show a noise voltage level of 450 nV/√Hz at 10 Hz, a temperature coefficient of 14 ppm/K and a PSRR of 52 dB.","PeriodicalId":6616,"journal":{"name":"2014 International Semiconductor Conference (CAS)","volume":"58 3 1","pages":"247-250"},"PeriodicalIF":0.0000,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 International Semiconductor Conference (CAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMICND.2014.6966450","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A novel architecture for a bandgap voltage reference is presented in this paper. The voltage reference, designed for image sensor applications, is primarily targeted for a low-noise operation along with other practical constraints such as high power supply rejection, temperature immunity and short start-up time. The analysis and operation of the circuit is discussed and the trade-offs involved in the implementation aspects are examined. The measurement results of the fabricated circuit in a 0.35-μm CMOS process show a noise voltage level of 450 nV/√Hz at 10 Hz, a temperature coefficient of 14 ppm/K and a PSRR of 52 dB.