Pub Date : 2014-12-01DOI: 10.1109/SMICND.2014.6966419
C. Ravariu, F. Babarada, E. Manea, C. Parvulescu, I. Rusu, I. Enache, M. Cristea, J. Arhip
The usual electrodes from electrophysiology are resistive. A variable metal-skin contact resistance frequently generates unpleasant artifacts. The capacitive electrodes avoid this disadvantage and are suitable for variable biosignals recording. The main novelty of this paper is the manufacturing of capacitive electrodes with all terminals on the top surface, letting free the electrode bottom for physiological preparations. So, the paper firstly presents the TCAD techniques used for the design of some capacitive electrode using three mask levels. By EDA, L-EDIT tools, the layers that constitute the fabrication masks are transferred to the glass support. In the last part, the electrodes technological flow design and testing in a real electrophysiological platform using the capacitive electrodes, are presented.
{"title":"Manufacturing of capacitive electrodes on Si-substrate for electrophysiological applications","authors":"C. Ravariu, F. Babarada, E. Manea, C. Parvulescu, I. Rusu, I. Enache, M. Cristea, J. Arhip","doi":"10.1109/SMICND.2014.6966419","DOIUrl":"https://doi.org/10.1109/SMICND.2014.6966419","url":null,"abstract":"The usual electrodes from electrophysiology are resistive. A variable metal-skin contact resistance frequently generates unpleasant artifacts. The capacitive electrodes avoid this disadvantage and are suitable for variable biosignals recording. The main novelty of this paper is the manufacturing of capacitive electrodes with all terminals on the top surface, letting free the electrode bottom for physiological preparations. So, the paper firstly presents the TCAD techniques used for the design of some capacitive electrode using three mask levels. By EDA, L-EDIT tools, the layers that constitute the fabrication masks are transferred to the glass support. In the last part, the electrodes technological flow design and testing in a real electrophysiological platform using the capacitive electrodes, are presented.","PeriodicalId":6616,"journal":{"name":"2014 International Semiconductor Conference (CAS)","volume":"108 1","pages":"151-154"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79336349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/SMICND.2014.6966379
L. Pierantoni, D. Mencarelli, M. Bozzi, R. Moro, A. Sindona, L. Spurio, S. Bellucci
We report on multiphysics full-wave techniques in the frequency (energy)-domain and time-domain, aimed at the investigation of the combined electromagnetic-coherent transport problem in nano-structured materials and devices, in particular carbon-based materials/devices. The quantum transport is modeled by i) discrete Hamiltonians at atomistic scale, ii) Schrödinger equation, and/or Dirac/Dirac-like eqs. at continuous level. In the frequency-domain, a rigorous Poisson-coherent transport equation system is provided. In the time-domain, Maxwell equations are self-consistently coupled to the Schrödinger/Dirac equations.
{"title":"Full-wave techniques for the electromagnetic-quantum transport modeling in nano-devices","authors":"L. Pierantoni, D. Mencarelli, M. Bozzi, R. Moro, A. Sindona, L. Spurio, S. Bellucci","doi":"10.1109/SMICND.2014.6966379","DOIUrl":"https://doi.org/10.1109/SMICND.2014.6966379","url":null,"abstract":"We report on multiphysics full-wave techniques in the frequency (energy)-domain and time-domain, aimed at the investigation of the combined electromagnetic-coherent transport problem in nano-structured materials and devices, in particular carbon-based materials/devices. The quantum transport is modeled by i) discrete Hamiltonians at atomistic scale, ii) Schrödinger equation, and/or Dirac/Dirac-like eqs. at continuous level. In the frequency-domain, a rigorous Poisson-coherent transport equation system is provided. In the time-domain, Maxwell equations are self-consistently coupled to the Schrödinger/Dirac equations.","PeriodicalId":6616,"journal":{"name":"2014 International Semiconductor Conference (CAS)","volume":"46 1","pages":"11-16"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87115354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/SMICND.2014.6966431
E. Ceuca, G. Brezeanu
This paper present the experimental case-study, concerning the behavior of wireless charging concept. The paper describes the experimental steps and tests to obtain a functional stand in order to understand and improve the design and achieve an optimal operation for the circuits involved in practical applications.
{"title":"Practical behavior of charging applications and command strategy in wireless power supplies","authors":"E. Ceuca, G. Brezeanu","doi":"10.1109/SMICND.2014.6966431","DOIUrl":"https://doi.org/10.1109/SMICND.2014.6966431","url":null,"abstract":"This paper present the experimental case-study, concerning the behavior of wireless charging concept. The paper describes the experimental steps and tests to obtain a functional stand in order to understand and improve the design and achieve an optimal operation for the circuits involved in practical applications.","PeriodicalId":6616,"journal":{"name":"2014 International Semiconductor Conference (CAS)","volume":"6 1","pages":"189-192"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87733107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/SMICND.2014.6966381
B. Șerban, M. Brezeanu, C. Cobianu, S. Costea, O. Buiu, Alisa Stratulat, N. Varachiu
This paper introduces the Hard Soft Acid Base (HSAB) concept as a promising tool for the selection of gas sensing layers. Target gas molecule - sensitive layer tandems are discussed and interpreted in the terms of this theory. Sensing layers suitable for carbon dioxide, nitrogen dioxide, sulphur dioxide, and hydrogen sulphide detection are presented and classified according to this concept. For oxygen and mineral acids detection, an indirect HSAB approach is discussed. The paper explains how the HSAB principle can be useful in designing gas sensing layers for different types of sensing structures, such as: surface acoustic waves (SAW), colorimetric, chemoresistive, etc.
{"title":"Materials selection for gas sensing. An HSAB perspective","authors":"B. Șerban, M. Brezeanu, C. Cobianu, S. Costea, O. Buiu, Alisa Stratulat, N. Varachiu","doi":"10.1109/SMICND.2014.6966381","DOIUrl":"https://doi.org/10.1109/SMICND.2014.6966381","url":null,"abstract":"This paper introduces the Hard Soft Acid Base (HSAB) concept as a promising tool for the selection of gas sensing layers. Target gas molecule - sensitive layer tandems are discussed and interpreted in the terms of this theory. Sensing layers suitable for carbon dioxide, nitrogen dioxide, sulphur dioxide, and hydrogen sulphide detection are presented and classified according to this concept. For oxygen and mineral acids detection, an indirect HSAB approach is discussed. The paper explains how the HSAB principle can be useful in designing gas sensing layers for different types of sensing structures, such as: surface acoustic waves (SAW), colorimetric, chemoresistive, etc.","PeriodicalId":6616,"journal":{"name":"2014 International Semiconductor Conference (CAS)","volume":"2015 1","pages":"21-30"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86986451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/SMICND.2014.6966378
M. Pfost
Advanced power semiconductors such as DMOS transistors are key components of modern power electronic systems. Recent discrete and integrated DMOS technologies have very low area-specific on-state resistances so that devices with small sizes can be chosen. However, their power dissipation can sometimes be large, for example in fault conditions, causing the device temperature to rise significantly. This can lead to excessive temperatures, reduced lifetime, and possibly even thermal runaway and subsequent destruction. Therefore, it is required to ensure already in the design phase that the temperature always remains in an acceptable range. This paper will show how self-heating in DMOS transistors can be experimentally determined with high accuracy. Further, it will be discussed how numerical electrothermal simulations can be carried out efficiently, allowing the accurate assessment of self-heating within a few minutes. The presented approach has been successfully verified experimentally for device temperatures exceeding 500°C up to the onset of thermal runaway.
{"title":"Characterization and modeling of self-heating in DMOS transistors","authors":"M. Pfost","doi":"10.1109/SMICND.2014.6966378","DOIUrl":"https://doi.org/10.1109/SMICND.2014.6966378","url":null,"abstract":"Advanced power semiconductors such as DMOS transistors are key components of modern power electronic systems. Recent discrete and integrated DMOS technologies have very low area-specific on-state resistances so that devices with small sizes can be chosen. However, their power dissipation can sometimes be large, for example in fault conditions, causing the device temperature to rise significantly. This can lead to excessive temperatures, reduced lifetime, and possibly even thermal runaway and subsequent destruction. Therefore, it is required to ensure already in the design phase that the temperature always remains in an acceptable range. This paper will show how self-heating in DMOS transistors can be experimentally determined with high accuracy. Further, it will be discussed how numerical electrothermal simulations can be carried out efficiently, allowing the accurate assessment of self-heating within a few minutes. The presented approach has been successfully verified experimentally for device temperatures exceeding 500°C up to the onset of thermal runaway.","PeriodicalId":6616,"journal":{"name":"2014 International Semiconductor Conference (CAS)","volume":"38 1","pages":"3-10"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74946140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/SMICND.2014.6966436
Pavel Brinzoi, Razvan Puccacu, Laurentiu Creocteanu
This paper presents a design solution for a high precision current-shunt monitor allowing input common-mode levels from -0.3V to 30V, independent of the supply voltage. The maximum referred to input offset voltage is ±10μV, over the entire common-mode input range. The proposed configuration has a fixed gain of 200 and exhibits a maximum gain error of 0.1%. The supply voltage can vary between 2.6V and 30V. The circuit has been designed in a 0.25μm BCD technology with a die area of only 0.8mm2.
{"title":"High precision current-shunt monitor with extended input common-mode voltage range","authors":"Pavel Brinzoi, Razvan Puccacu, Laurentiu Creocteanu","doi":"10.1109/SMICND.2014.6966436","DOIUrl":"https://doi.org/10.1109/SMICND.2014.6966436","url":null,"abstract":"This paper presents a design solution for a high precision current-shunt monitor allowing input common-mode levels from -0.3V to 30V, independent of the supply voltage. The maximum referred to input offset voltage is ±10μV, over the entire common-mode input range. The proposed configuration has a fixed gain of 200 and exhibits a maximum gain error of 0.1%. The supply voltage can vary between 2.6V and 30V. The circuit has been designed in a 0.25μm BCD technology with a die area of only 0.8mm2.","PeriodicalId":6616,"journal":{"name":"2014 International Semiconductor Conference (CAS)","volume":"107 1","pages":"203-206"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79274703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/SMICND.2014.6966450
I. Subbiah, Andreas Suss, A. Kravchenko, B. Hosticka, W. Krautschneider
A novel architecture for a bandgap voltage reference is presented in this paper. The voltage reference, designed for image sensor applications, is primarily targeted for a low-noise operation along with other practical constraints such as high power supply rejection, temperature immunity and short start-up time. The analysis and operation of the circuit is discussed and the trade-offs involved in the implementation aspects are examined. The measurement results of the fabricated circuit in a 0.35-μm CMOS process show a noise voltage level of 450 nV/√Hz at 10 Hz, a temperature coefficient of 14 ppm/K and a PSRR of 52 dB.
{"title":"A low-noise saturation-stacked bandgap reference for image sensor applications","authors":"I. Subbiah, Andreas Suss, A. Kravchenko, B. Hosticka, W. Krautschneider","doi":"10.1109/SMICND.2014.6966450","DOIUrl":"https://doi.org/10.1109/SMICND.2014.6966450","url":null,"abstract":"A novel architecture for a bandgap voltage reference is presented in this paper. The voltage reference, designed for image sensor applications, is primarily targeted for a low-noise operation along with other practical constraints such as high power supply rejection, temperature immunity and short start-up time. The analysis and operation of the circuit is discussed and the trade-offs involved in the implementation aspects are examined. The measurement results of the fabricated circuit in a 0.35-μm CMOS process show a noise voltage level of 450 nV/√Hz at 10 Hz, a temperature coefficient of 14 ppm/K and a PSRR of 52 dB.","PeriodicalId":6616,"journal":{"name":"2014 International Semiconductor Conference (CAS)","volume":"58 3 1","pages":"247-250"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79802563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/SMICND.2014.6966389
C. Palade, A. Lepadatu, I. Stavarache, V. Teodorescu, M. Ciurea
GeSi-based nanostructures show unique properties which make them suitable for integrated circuit technology. The strong interest is to enhance their electronic properties in order to improve the device performance. In order to obtain fundamental knowledge on the electrical transport taking place in GeSi nanostructures we have investigated the effects of different microstructures on the electrical behavior of GeSi nanostructured films, by modifying the annealing conditions. We manufactured GeSi nanostructured films with equiatomic composition and different structures by co-sputtering followed by adequate annealing under different temperatures. For determining the electrical behavior we performed and modeled current-temperature I - T characteristics taking into account the films structures. We found that the electrical behavior changes with the film structure by evidencing a transition in conduction mechanism. In films that are almost crystallized, being formed of small GeSi nanocrystals separated by thin amorphous regions, the I - T dependence at low temperature is due to thermally activated tunneling of carriers between neighboring nanocrystals. In contrast, in the completely crystallized films with big GeSi nanocrystals and crystallized borders between them, the electrical behavior is a typical polycrystalline one. Our findings help to clarify the conduction mechanisms taking place in GeSi nanostructures and to provide a route to electronic devices with high performance based on these materials.
{"title":"Transition in conduction mechanism in GeSi nanostructures","authors":"C. Palade, A. Lepadatu, I. Stavarache, V. Teodorescu, M. Ciurea","doi":"10.1109/SMICND.2014.6966389","DOIUrl":"https://doi.org/10.1109/SMICND.2014.6966389","url":null,"abstract":"GeSi-based nanostructures show unique properties which make them suitable for integrated circuit technology. The strong interest is to enhance their electronic properties in order to improve the device performance. In order to obtain fundamental knowledge on the electrical transport taking place in GeSi nanostructures we have investigated the effects of different microstructures on the electrical behavior of GeSi nanostructured films, by modifying the annealing conditions. We manufactured GeSi nanostructured films with equiatomic composition and different structures by co-sputtering followed by adequate annealing under different temperatures. For determining the electrical behavior we performed and modeled current-temperature I - T characteristics taking into account the films structures. We found that the electrical behavior changes with the film structure by evidencing a transition in conduction mechanism. In films that are almost crystallized, being formed of small GeSi nanocrystals separated by thin amorphous regions, the I - T dependence at low temperature is due to thermally activated tunneling of carriers between neighboring nanocrystals. In contrast, in the completely crystallized films with big GeSi nanocrystals and crystallized borders between them, the electrical behavior is a typical polycrystalline one. Our findings help to clarify the conduction mechanisms taking place in GeSi nanostructures and to provide a route to electronic devices with high performance based on these materials.","PeriodicalId":6616,"journal":{"name":"2014 International Semiconductor Conference (CAS)","volume":"1 1","pages":"55-58"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81716604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/SMICND.2014.6966451
Iustin-Catalin Necula, C. Popa
This paper describes a bandgap voltage reference with second order curvature correction which utilizes a cvasi-independent temperature current and a Buck voltage transfer cell to compensate the non-linear term of the VBE's expression. The proposed circuit is implemented in a 0.35um CMOS technology and achieves a 2.36ppm/ C temperature coefficient (TC) in a temperature range from -40 to 150 C. The nominal supply voltage is 3V and the consumed power is 558uW. The power supply rejection ratio (PSRR) is -50dB at 10kHz and -30dB at 100kHz.
{"title":"Voltage reference with second order curvature correction","authors":"Iustin-Catalin Necula, C. Popa","doi":"10.1109/SMICND.2014.6966451","DOIUrl":"https://doi.org/10.1109/SMICND.2014.6966451","url":null,"abstract":"This paper describes a bandgap voltage reference with second order curvature correction which utilizes a cvasi-independent temperature current and a Buck voltage transfer cell to compensate the non-linear term of the VBE's expression. The proposed circuit is implemented in a 0.35um CMOS technology and achieves a 2.36ppm/ C temperature coefficient (TC) in a temperature range from -40 to 150 C. The nominal supply voltage is 3V and the consumed power is 558uW. The power supply rejection ratio (PSRR) is -50dB at 10kHz and -30dB at 100kHz.","PeriodicalId":6616,"journal":{"name":"2014 International Semiconductor Conference (CAS)","volume":"37 1","pages":"251-254"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77714822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/SMICND.2014.6966439
C. Stănescu, C. Dinca, R. Iacob
The paper presents a symmetrical passive RC notch filter with two cutoff frequencies used for ripple reduction in chopper offset-stabilized amplifiers. The filter has two cutoff frequencies: the first one is the chopping frequency itself, while the second one is the third harmonic. The rejection of the proposed filter is 60 dB around the cutoff frequencies. The chopping frequency is correlated with the cutoff frequencies by using a current-driven oscillator and a bias circuit using the same type of resistor as the filter itself. A circuit using this technique was fabricated, achieving a low-frequency noise performance of 1.3 μVpp.
{"title":"Symmetrical passive RC notch filter with two cutoff frequencies for ripple reduction in chopper offset-stabilized amplifiers","authors":"C. Stănescu, C. Dinca, R. Iacob","doi":"10.1109/SMICND.2014.6966439","DOIUrl":"https://doi.org/10.1109/SMICND.2014.6966439","url":null,"abstract":"The paper presents a symmetrical passive RC notch filter with two cutoff frequencies used for ripple reduction in chopper offset-stabilized amplifiers. The filter has two cutoff frequencies: the first one is the chopping frequency itself, while the second one is the third harmonic. The rejection of the proposed filter is 60 dB around the cutoff frequencies. The chopping frequency is correlated with the cutoff frequencies by using a current-driven oscillator and a bias circuit using the same type of resistor as the filter itself. A circuit using this technique was fabricated, achieving a low-frequency noise performance of 1.3 μVpp.","PeriodicalId":6616,"journal":{"name":"2014 International Semiconductor Conference (CAS)","volume":"430 1","pages":"215-218"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89934683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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