Transparent mode flip-flops for collapsible pipelines

Eric L. Hill, Mikko H. Lipasti
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引用次数: 4

Abstract

Prior work has shown that collapsible pipelining techniques have the potential to significantly reduce clocking activity, which can consume up to 70% of the dynamic power in modern high performance microprocessors. Previous collapsible pipeline proposals either rely on single phase clocking (by forcing latches into transparent state) or do not discuss the mechanisms by which stages are merged. In this work two flip-flop designs featuring an additional transparent state suitable for collapsing stages are presented. Transparency is achieved either by decoupling the master and slave clocks to keep both latches transparent, or by using a bypass mux that routes around the flip-flop. Both of these designs are evaluated in the context of transparently gated pipelines, an ad-hoc collapsible pipelining technique. Detailed analysis shows that the decoupled clock flip-flop is the most attractive in terms of energy and delay.
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可折叠管道的透明模式人字拖
先前的研究表明,可折叠的流水线技术有可能显著减少时钟活动,这可能会消耗现代高性能微处理器中高达70%的动态功率。以前的可折叠管道提案要么依赖于单相时钟(通过迫使锁存器进入透明状态),要么没有讨论阶段合并的机制。在这项工作中,提出了两种具有适合折叠阶段的额外透明状态的触发器设计。通过将主时钟和从时钟解耦以保持两个锁存器透明,或者通过使用绕过触发器的旁路复用器来实现透明度。这两种设计都是在透明门控管道的背景下进行评估的,透明门控管道是一种特殊的可折叠管道技术。详细分析表明,解耦时钟触发器在能量和延迟方面最具吸引力。
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