M. Pereira, J. Vaz, C. Leme, J. Sousa, J. C. Freire
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引用次数: 4
Abstract
This paper presents a digital low-IF Gaussian frequency-shift keying (GFSK) demodulator. The demodulator is based on a phase-shift quadrature discriminator. A preamble detector controls the sequencing of the blocks operation to minimize power consumption. An IF input signal of 1 MHz is used, the same of the data rate, hence, allowing a low-power receiver implementation. The implementation is fully digital with a silicon area of 0.06 mm2 in 130 nm process. Simulations show a state-of-art current consumption of about 143 μA from a single 1.2 V supply voltage. The proposed demodulator requires a SNR of 15 dB for a BER of 0.1 % for up to ± 200 kHz frequency offset variation.