{"title":"A new design for complete on-chip ESD protection","authors":"Albert Z. H. Wang","doi":"10.1109/CICC.2000.852624","DOIUrl":null,"url":null,"abstract":"The design of a novel compact Electrostatic Discharge (ESD) protection structure is reported. It provides complete ESD protection in all directions, i.e. positive/negative from I/O to power supply V/sub DD/, positive/negative from I/O to ground, and from V/sub DD/ to ground. This ultra-fast (t/sub 1//spl sim/0.16 nS) structure operates symmetrically. Measurements showed low holding voltage (/spl sim/2 V), low discharging impedance (/spl sim//spl Omega/), and adjustable triggering voltages. ESD tests passed 14 kV (HBM). Design prediction was achieved by comprehensive ESD simulation. It is particularly good for RF ICs.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"22 1","pages":"87-90"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2000.852624","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
The design of a novel compact Electrostatic Discharge (ESD) protection structure is reported. It provides complete ESD protection in all directions, i.e. positive/negative from I/O to power supply V/sub DD/, positive/negative from I/O to ground, and from V/sub DD/ to ground. This ultra-fast (t/sub 1//spl sim/0.16 nS) structure operates symmetrically. Measurements showed low holding voltage (/spl sim/2 V), low discharging impedance (/spl sim//spl Omega/), and adjustable triggering voltages. ESD tests passed 14 kV (HBM). Design prediction was achieved by comprehensive ESD simulation. It is particularly good for RF ICs.
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