An ultra-low power and offset-insensitive CMOS subthreshold voltage reference

Lidan Wang, Chenchang Zhan, Guofeng Li
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引用次数: 1

Abstract

An ultra-low power and offset-insensitive CMOS voltage reference circuit is presented. Due to the novel structure of employing subthreshold MOS transistors, the proposed circuit can suppress the DC offset effects of the internal amplifier. Design considerations in optimizing the power and area consumptions, and improving the power supply ripple rejection (PSRR) are presented. The voltage reference is implemented in a 0.18μm CMOS process. Simulation results show that the reference can run with 0.8 V supply voltage, while the power consumption is only 62nW, and the PSRR of better than −43 dB over the full frequency range is achieved.
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超低功耗和偏置不敏感的CMOS亚阈值电压基准
提出了一种超低功耗、偏置不敏感的CMOS电压基准电路。由于采用亚阈值MOS晶体管的新颖结构,该电路可以抑制内部放大器的直流偏置效应。提出了优化功耗和面积消耗以及提高电源纹波抑制(PSRR)的设计考虑。基准电压采用0.18μm CMOS工艺。仿真结果表明,该基准电路可以在0.8 V电源电压下运行,功耗仅为62nW,在全频率范围内的PSRR优于−43 dB。
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