A 2-clock-cycle Naïve Bayes classifier for dynamic branch prediction in pipelined RISC microprocessors

Itaru Hida, M. Ikebe, T. Asai, M. Motomura
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引用次数: 1

Abstract

In this paper, we propose a Bayesian branch-prediction circuit consisting of an instruction-feature extractor and a naïve Bayes classifier (NBC). Its purpose is to replace conventional branch predictors in modern pipelined RISC microprocessors. The proposed circuit is based on the conventional neural branch predictor [1]; however, the linear classifier circuit is replaced by the proposed NBC circuit. Implementing approximate Bayesian computation and its highly-parallel architectures, the NBC circuit completes branch prediction within 2 clock cycles per instruction, and is this suitable for implementation on standard pipelined microprocessors.
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一个2时钟周期Naïve贝叶斯分类器动态分支预测在流水线RISC微处理器
本文提出了一种由指令特征提取器和naïve贝叶斯分类器(NBC)组成的贝叶斯分支预测电路。它的目的是取代传统的分支预测器在现代流水线RISC微处理器。该电路基于传统的神经分支预测器[1];然而,线性分类器电路被提议的NBC电路所取代。NBC电路实现近似贝叶斯计算及其高度并行架构,每条指令在2个时钟周期内完成支路预测,适合在标准流水线微处理器上实现。
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