{"title":"A 2-clock-cycle Naïve Bayes classifier for dynamic branch prediction in pipelined RISC microprocessors","authors":"Itaru Hida, M. Ikebe, T. Asai, M. Motomura","doi":"10.1109/APCCAS.2016.7803958","DOIUrl":null,"url":null,"abstract":"In this paper, we propose a Bayesian branch-prediction circuit consisting of an instruction-feature extractor and a naïve Bayes classifier (NBC). Its purpose is to replace conventional branch predictors in modern pipelined RISC microprocessors. The proposed circuit is based on the conventional neural branch predictor [1]; however, the linear classifier circuit is replaced by the proposed NBC circuit. Implementing approximate Bayesian computation and its highly-parallel architectures, the NBC circuit completes branch prediction within 2 clock cycles per instruction, and is this suitable for implementation on standard pipelined microprocessors.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS.2016.7803958","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
In this paper, we propose a Bayesian branch-prediction circuit consisting of an instruction-feature extractor and a naïve Bayes classifier (NBC). Its purpose is to replace conventional branch predictors in modern pipelined RISC microprocessors. The proposed circuit is based on the conventional neural branch predictor [1]; however, the linear classifier circuit is replaced by the proposed NBC circuit. Implementing approximate Bayesian computation and its highly-parallel architectures, the NBC circuit completes branch prediction within 2 clock cycles per instruction, and is this suitable for implementation on standard pipelined microprocessors.