Advanced low profile PoP solution with embedded wafer level PoP (eWLB-PoP) technology

S. Yoon, Jose Alvin Caparas, Yaojian Lin, P. Marimuthu
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引用次数: 46

Abstract

Current portable electronic products are driving component packaging towards 3D packaging technologies for integrating multiple memory die and application processors (AP). Among the 3D technologies, Package-on-Package (PoP) is increasingly becoming mainstream due to its flexibility of combination and sourcing. Moreover, device designs require functional integration of IC's, especially in the 3rd dimension, hence driving new technology development towards making IC components “thin and thinner”. eWLB (embedded Wafer Level Ball Grid Array) has been introduced into production to allow for higher ball count WLP, by extending the package size beyond the area of the chip. There is also great opportunity related to a 3D variation of eWLB which would allow for mounting of components or another package on the top surface with thinner profile and Package-on-Package (eWBL-PoP) technology. 3D PoP-eWLB is envisioned as an exciting technology which will open up the floodgates for system level integration utilizing very thin stacked eWLB packages as building blocks in mobile applications. This paper reports developments that are aimed to extend the low profile PoP application with eWLB + PoP technology. Test vehicle is designed and fabricated to demonstrate to be thin and 3D PoP solution for mobile and portable electronics. Assembly process details including laser ablation and interconnects process and mechanical characterizations are to be discussed with component and board level reliability results. Innovative package structures optimization that provide dual advantages of both form factor reduction and enhanced package reliability are reported. To enable higher interconnection density and signal routing, package with multi layer redistribution (RDL) and 10um/10um line width/spacing is fabricated and implemented on eWLB platform. Successful reliability characterization results on low profile PoP package configurations are reported that demonstrate eWLB-PoP as an enabling technology for miniaturized, low profile and cost-effective 3D PoP.
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采用嵌入式晶圆级PoP (eWLB-PoP)技术的先进低姿态PoP解决方案
目前的便携式电子产品正在推动组件封装向集成多个存储芯片和应用处理器(AP)的3D封装技术发展。在3D技术中,包对包(PoP)由于其组合和采购的灵活性正日益成为主流。此外,器件设计需要集成电路的功能集成,特别是在三维空间,因此推动了新技术的发展,使集成电路组件“越来越薄”。嵌入式晶圆级球栅阵列(eWLB)已经投入生产,通过将封装尺寸扩展到芯片面积之外,可以实现更高的球数WLP。eWLB的3D变化也有很大的机会,它允许在顶部表面安装组件或另一个封装,具有更薄的轮廓和封装上封装(eWBL-PoP)技术。3D PoP-eWLB被认为是一项令人兴奋的技术,它将打开系统级集成的闸门,利用非常薄的堆叠eWLB包作为移动应用程序的构建块。本文介绍了利用eWLB + PoP技术扩展低功耗PoP应用的研究进展。测试车辆的设计和制造是为了展示移动和便携式电子产品的薄和3D PoP解决方案。装配工艺细节,包括激光烧蚀和互连工艺和机械特性,将与组件和板级可靠性结果进行讨论。创新的封装结构优化提供了双重优势,既减少了外形因素,又提高了封装的可靠性。为了实现更高的互连密度和信号路由,在eWLB平台上制作并实现了具有多层再分布(RDL)和10um/10um线宽/间距的封装。据报道,在低尺寸PoP封装配置上成功的可靠性表征结果表明,eWLB-PoP是一种小型化、低尺寸且具有成本效益的3D PoP技术。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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Parasitic electrical and electromagnetic effects Heat management Passive electronic components Interconnection technology Reliability and maintainability
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