An efficient framework for design and assessment of arithmetic operators with Reduced-Precision Redundancy

Abstract

For arithmetic circuits, Reduced-Precision Redundancy (RPR) is considered to be a viable alternative to Triple Modular Redundancy (TMR), as it offers significant power reduction. However, efficient implementation and assessment of hardware arithmetic operators with RPR is still a challenge. In this work we propose a lightweight RPR design methodology that exploits the capabilities of modern synthesis and simulation tools to simplify the design and verification of robust arithmetic operators. To demonstrate the effectiveness of the proposed framework we apply it to implement and compare two commonly used RPR schemes. Our experimental results show that the proposed framework simplifies the design and provides robustness indicators with a maximum coefficient of variation of 14.7% with a 3× experimentation speed-up at a cost of 25% computational effort compared to an exhaustive approach.