Study of low temperature and high heat-resistant fluxless bonding via nanoscale thin film control toward wafer-level multiple chip stacking for 3D LSI

E. Morinaga, Y. Oka, H. Nishimori, H. Miyagawa, R. Satoh, Y. Iwata, R. Kanezaki
{"title":"Study of low temperature and high heat-resistant fluxless bonding via nanoscale thin film control toward wafer-level multiple chip stacking for 3D LSI","authors":"E. Morinaga, Y. Oka, H. Nishimori, H. Miyagawa, R. Satoh, Y. Iwata, R. Kanezaki","doi":"10.1109/ECTC.2012.6248799","DOIUrl":null,"url":null,"abstract":"The three dimensional system in package (3D-SiP) has been regarded as a promising solution to the scaling limit problem in the semiconductor industry. Practical realization of the 3D-SiP needs establishing a standard bonding technology for chip stacking. This research focuses on a low temperature and high heat-resistant fluxless bonding method, which can overcome the bump height variation problem in a chip/wafer, using high-boiling alcohol, an indium-tin (InSn) thin film and its transformation into high-melting intermetallic compound (IMC). Experimental studies showed high-rate deposition of InSn alloy and successive deposition of silver achieve successful bonding where the joint has high melting point (higher than 673K).","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"4 1","pages":"14-19"},"PeriodicalIF":0.0000,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE 62nd Electronic Components and Technology Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.2012.6248799","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

Abstract

The three dimensional system in package (3D-SiP) has been regarded as a promising solution to the scaling limit problem in the semiconductor industry. Practical realization of the 3D-SiP needs establishing a standard bonding technology for chip stacking. This research focuses on a low temperature and high heat-resistant fluxless bonding method, which can overcome the bump height variation problem in a chip/wafer, using high-boiling alcohol, an indium-tin (InSn) thin film and its transformation into high-melting intermetallic compound (IMC). Experimental studies showed high-rate deposition of InSn alloy and successive deposition of silver achieve successful bonding where the joint has high melting point (higher than 673K).
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
三维大规模集成电路晶圆级多芯片堆叠的纳米级薄膜控制低温高耐热无熔合研究
三维封装系统(3D-SiP)被认为是解决半导体行业缩放限制问题的一种很有前途的方法。3D-SiP的实际实现需要建立一种标准的芯片堆叠键合技术。本研究利用高沸点醇、铟锡(InSn)薄膜及其转化为高熔点金属间化合物(IMC),研究了一种克服芯片/晶圆中凹凸高度变化问题的低温高耐热无熔点键合方法。实验研究表明,在高熔点处(大于673K),高速率沉积InSn合金和连续沉积银可以成功结合。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Parasitic electrical and electromagnetic effects Heat management Passive electronic components Interconnection technology Reliability and maintainability
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1