"Hole-in-One TSV", a New Via Last Concept for High Density 3D-SOC Interconnects

Abstract

This paper presents face-to-face wafer-to-wafer (W2W) bonding using SiCN-to-SiCN dielectric bonding, in combination a novel 1µm diameter via last connection between top and bottom wafers, called "hole-in-one TSV". This scheme reduces besides the interconnection pitch and also the number of processing steps. The hole-in-one TSV is introducing an innovating integration modification. With the introduction of a cavity etched in the top wafer prior to W2W bonding, the via last etch process is simplified. The etch time of the dielectric part of the TSV etch is heavily reduced, minimizing the over etch time on the top landing metal to open the landing wafer's metal pad. Critical integration steps like CMP processes, wafer bonding and thinning to 5µm Si thickness are highlighted, together with alignment tolerances and connectivity yield between the bonded 300mm Si wafers.