Pub Date : 2018-11-01DOI: 10.1109/ICSJ.2018.8602655
Wei-chung Chen, C. Lee, H. Kuo, Min-Hua Chung, Chaung-Chi Wang, Shang-Kun Huang, Yen-Sen Liao, Chen-Chao Wang, D. Tarng
Development of 2.1D package with organic interposer in panel size based on the high resolution dry film photoresist and the ultra-thin electro-less copper seed layer will be reported in this paper. The aim of 2.1D technology is focus on the reducing of production cost and increase I/O counts simultaneously. Compare to the wafer level lithography process, substrate-based process leads to the benefit in cost reduction and risk elusion form chip first process. The high resolution photolithography semi-additive processes (SAP) can achieve 3 µm copper line width and 25 µm laser drilled vias in panel size (510*408mm). On the other hand, the sputtered metal seed layer can be replaced by electro-less copper plating seed layer (approximately 0.1 µm). When it comes to cost, dry film photoresist and electro-less copper seed layer processes can significantly save the equipment and material cost compared to the wafer patterning process. These high density interconnection lines, micro-bump pads and vias are integrated and demonstrated on an organic film in the thickness of 25 µm. Micro-bump pads designed for the copper pillar bond are with a 25 µm diameter and a 40 µm pitch. Flip chip bond alignment is verified by the x-ray examination. The embedded trace substrate (ETS) by using plating nickel thin layer for etching resistance, copper trace with 3 µm width and spacing embedded in the organic film can be formed with very good flatness performance. Moreover, this designed 2.1D organic interposer substrate has passed the MSL3 (Moisture Soaking Level 3) standard and the TCT (Thermal Cycling Test) reliability test with 1000 cycles. In terms of electrical property study, kinds of dielectric materials and high resolution photoresists are employed in this study. The electrical measurement including DC resistance and S-parameter is performed to tell apart the different performance of dielectric and photoresist materials, and the result show agreement with the formed appearance of copper traces.
{"title":"Development of Novel Fine Line 2.1 D Package with Organic Interposer Using Advanced Substrate-Based Process","authors":"Wei-chung Chen, C. Lee, H. Kuo, Min-Hua Chung, Chaung-Chi Wang, Shang-Kun Huang, Yen-Sen Liao, Chen-Chao Wang, D. Tarng","doi":"10.1109/ICSJ.2018.8602655","DOIUrl":"https://doi.org/10.1109/ICSJ.2018.8602655","url":null,"abstract":"Development of 2.1D package with organic interposer in panel size based on the high resolution dry film photoresist and the ultra-thin electro-less copper seed layer will be reported in this paper. The aim of 2.1D technology is focus on the reducing of production cost and increase I/O counts simultaneously. Compare to the wafer level lithography process, substrate-based process leads to the benefit in cost reduction and risk elusion form chip first process. The high resolution photolithography semi-additive processes (SAP) can achieve 3 µm copper line width and 25 µm laser drilled vias in panel size (510*408mm). On the other hand, the sputtered metal seed layer can be replaced by electro-less copper plating seed layer (approximately 0.1 µm). When it comes to cost, dry film photoresist and electro-less copper seed layer processes can significantly save the equipment and material cost compared to the wafer patterning process. These high density interconnection lines, micro-bump pads and vias are integrated and demonstrated on an organic film in the thickness of 25 µm. Micro-bump pads designed for the copper pillar bond are with a 25 µm diameter and a 40 µm pitch. Flip chip bond alignment is verified by the x-ray examination. The embedded trace substrate (ETS) by using plating nickel thin layer for etching resistance, copper trace with 3 µm width and spacing embedded in the organic film can be formed with very good flatness performance. Moreover, this designed 2.1D organic interposer substrate has passed the MSL3 (Moisture Soaking Level 3) standard and the TCT (Thermal Cycling Test) reliability test with 1000 cycles. In terms of electrical property study, kinds of dielectric materials and high resolution photoresists are employed in this study. The electrical measurement including DC resistance and S-parameter is performed to tell apart the different performance of dielectric and photoresist materials, and the result show agreement with the formed appearance of copper traces.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"12 1","pages":"601-606"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79249735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study presents a novel modeling approach for wetness and moisture concentration in the presence of time dependent saturated moisture concentration by employing the traditional ANSYS thermal and surface effect elements. The accuracy of the present approach is established by comparison with those of the existing ANSYS “diffusion” and “coupled field” elements as well as peridynamic theory. The comparison concerns the desorption process in a fully saturated bar made of two different materials with equal and unequal values of solubility activation energy in the presence of time dependent saturated moisture concentration under uniform and nonuniform temperature conditions. The results from the present approach agree well with those of peridynamics and ANSYS “coupled field” elements if the diffusivity is specified as time dependent. Significant deviation occurs if the diffusivity is specified as temperature dependent. The ANSYS “diffusion” element is applicable only for uniform temperature, and deviation becomes significant especially for unequal values of solubility activation energy.
{"title":"A Novel Finite Element Technique for Moisture Diffusion Modeling Using ANSYS","authors":"C. Diyaroglu, S. Oterkus, E. Oterkus","doi":"10.1109/ECTC.2018.00043","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00043","url":null,"abstract":"This study presents a novel modeling approach for wetness and moisture concentration in the presence of time dependent saturated moisture concentration by employing the traditional ANSYS thermal and surface effect elements. The accuracy of the present approach is established by comparison with those of the existing ANSYS “diffusion” and “coupled field” elements as well as peridynamic theory. The comparison concerns the desorption process in a fully saturated bar made of two different materials with equal and unequal values of solubility activation energy in the presence of time dependent saturated moisture concentration under uniform and nonuniform temperature conditions. The results from the present approach agree well with those of peridynamics and ANSYS “coupled field” elements if the diffusivity is specified as time dependent. Significant deviation occurs if the diffusivity is specified as temperature dependent. The ANSYS “diffusion” element is applicable only for uniform temperature, and deviation becomes significant especially for unequal values of solubility activation energy.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"31 1","pages":"227-235"},"PeriodicalIF":0.0,"publicationDate":"2018-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81629659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Rajaguru, C. Bailey, Hua Lu, A. Castellazzi, M. Antonini, V. Pathirana, N. Udugampola, F. Udrea, Paul Mitchelson, S. Aldhaher
An assembly exercise was proposed to replace the vertical MOSFET by lateral IGBTs (LIGBT) for LED driver systems which can provide significant advantages in terms of size reduction (LIGBTs are ten times smaller than vertical MOSFETs) and lower component count. A 6 circle, 5V gate, 800 V LIGBT device with dimension of 818µm x 672µm with deposited solder balls that has a radius of around 75µm was selected in this assembly exercise. The driver system uses chip on board (COB) technique to create a compact driver system which can fit into a GU10 bulb housing. The challenging aspect of the LIGBT package in high voltage application is underfill dielectric breakdown and solder fatigue failure. In order to predict the extreme electric field values of the underfill, an electrostatic finite element analysis was undertaken on the LIGBT package structure for various underfill permittivity values. From the electro static finite element analysis, the maximum electric field in the underfill was estimated as 38 V/µm. Five commercial underfills were selected for investigating the trade-off in materials properties that mitigate underfill electrical breakdown and solder joint fatigue failure. These selected underfills have dielectric breakdown higher than the predicted value from electrostatic analysis. The thermo-mechanical finite element analysis were undertaken for solder bump reliability for all the underfill materials. The underfill which can enhance the solder reliability was chosen as prime candidate.
提出了一种组装练习，用LED驱动系统的横向igbt (light)取代垂直MOSFET，这可以在尺寸减小(light比垂直MOSFET小十倍)和更低的组件数量方面提供显着优势。在这次组装练习中，选择了一个6圈，5V栅极，800 V的light器件，尺寸为818 μ m x 672 μ m，沉积的焊球半径约为75 μ m。驱动系统使用板上芯片(COB)技术来创建一个紧凑的驱动系统，可以安装到GU10灯泡外壳中。light封装在高压应用中最具挑战性的方面是下填充介质击穿和焊料疲劳失效。为了预测下填料的极端电场值，对不同下填料介电常数下的light封装结构进行了静电有限元分析。通过静电有限元分析，估计下填区最大电场为38 V/µm。研究人员选择了五个商业底填土来研究减轻底填土电击穿和焊点疲劳失效的材料性能的权衡。所选下填土的介电击穿值高于静电分析的预测值。对各种底填材料的凸点可靠性进行了热-力学有限元分析。选择了能提高焊料可靠性的底填料作为首选材料。
{"title":"Mechanical Modelling of High Power Lateral IGBT for LED Driver Applications","authors":"P. Rajaguru, C. Bailey, Hua Lu, A. Castellazzi, M. Antonini, V. Pathirana, N. Udugampola, F. Udrea, Paul Mitchelson, S. Aldhaher","doi":"10.1109/ECTC.2018.00210","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00210","url":null,"abstract":"An assembly exercise was proposed to replace the vertical MOSFET by lateral IGBTs (LIGBT) for LED driver systems which can provide significant advantages in terms of size reduction (LIGBTs are ten times smaller than vertical MOSFETs) and lower component count. A 6 circle, 5V gate, 800 V LIGBT device with dimension of 818µm x 672µm with deposited solder balls that has a radius of around 75µm was selected in this assembly exercise. The driver system uses chip on board (COB) technique to create a compact driver system which can fit into a GU10 bulb housing. The challenging aspect of the LIGBT package in high voltage application is underfill dielectric breakdown and solder fatigue failure. In order to predict the extreme electric field values of the underfill, an electrostatic finite element analysis was undertaken on the LIGBT package structure for various underfill permittivity values. From the electro static finite element analysis, the maximum electric field in the underfill was estimated as 38 V/µm. Five commercial underfills were selected for investigating the trade-off in materials properties that mitigate underfill electrical breakdown and solder joint fatigue failure. These selected underfills have dielectric breakdown higher than the predicted value from electrostatic analysis. The thermo-mechanical finite element analysis were undertaken for solder bump reliability for all the underfill materials. The underfill which can enhance the solder reliability was chosen as prime candidate.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"27 1","pages":"1375-1381"},"PeriodicalIF":0.0,"publicationDate":"2018-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87301266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Electrochromic films have been used as a non-emissive material for display applications. Such materials have already been integrated in antiglare rearview mirrors for passenger vehicles as well as smart windows intended for energy savings for buildings. However, most electrochromic materials are deposited on rigid substrates, which prevent its use in flexible and stretchable electronic applications, where low temperature deposition techniques are desired. Additionally, electrochormics require an external power source to drive the underlying reduction/oxidation reaction. In this work, electrochromic materials inkjet-printed onto flexible and stretchable substrates have been explored. These devices are "self-powered" by organic solar cells also fabricated on flexible and stretchable substrate such as PDMS and PET. A set of inks based on a combination of synthesized and commercially obtained WO_3 nanoparticles, W-TiO_2 and TiO_2 nanoparticles were evaluated. The microstructure of the nanoparticles used in this study were examined under scanning electron microscopy for examining nanoparticle morphology, x-ray diffraction for chemical and structural characterization, and dynamic light scattering for particle size determination. Electrochromic layers were then ink-jet printed on flexible and stretchable PDMS substrates, using synthesized Ag nanowires as conductive, yet highly transparent electrodes. The stretchable printed electrochromic devices under various stress conditions and electrochromic performances were evaluated and demonstrated clear switching behavior under external bias, with 7 second coloration time, 8 second bleaching time, and 0.36-0.75 optical modulation at ?=525 nm. Cyclic voltammetry and galvanostatic charge/discharge measurements demonstrated high areal capacitance, with limited stability upon cycled operation. The electrochromic devices were then integrated in an Internet of Things (IoT)-enabled switching configuration, self-powered by PCDTBT:PC_70BM organic photovoltaics. The bulk heterojunction devices were evaluated with varying hole-transport layers and substrates, and exhibited the strongest performance of PCE? 3%, V_oc=0.9V and J_sc ? 10-15 mA/cm^2. The described self-powered, IoT-enabled, ink-jet printed electrochromic devices, fabricated on flexible substrates, are demonstrative of potential applications for wearable electronics.
电致变色薄膜已被用作显示应用的非发射材料。这种材料已经被集成到乘用车的防眩后视镜中，以及用于建筑节能的智能窗户中。然而，大多数电致变色材料沉积在刚性衬底上，这阻碍了其在需要低温沉积技术的柔性和可拉伸电子应用中的使用。此外，电化学需要外部电源来驱动潜在的还原/氧化反应。在这项工作中，电致变色材料喷墨印刷在柔性和可拉伸的基材上进行了探索。这些设备是由有机太阳能电池“自供电”的，有机太阳能电池也制造在柔性和可拉伸的衬底上，如PDMS和PET。对合成的WO_3纳米粒子、W-TiO_2纳米粒子和TiO_2纳米粒子复合制备的油墨进行了评价。本研究中使用的纳米颗粒的微观结构通过扫描电子显微镜检查纳米颗粒形态，x射线衍射检查化学和结构表征，动态光散射检查颗粒大小。然后将电致变色层喷墨印刷在柔性和可拉伸的PDMS衬底上，使用合成的银纳米线作为导电且高度透明的电极。在7秒显色时间、8秒漂白时间和0.36-0.75光调制波长为525 nm的条件下，对不同应力条件下的可拉伸电致变色印刷器件和电致变色性能进行了评估。循环伏安法和恒流充放电测量显示出高面电容，在循环操作时稳定性有限。然后将电致变色器件集成到支持物联网(IoT)的开关配置中，由pcdbt:PC_70BM有机光伏电池自供电。采用不同的空穴传输层和衬底对体异质结器件进行了评价，并表现出最强的PCE?3%， V_oc=0.9V, J_sc ?10 - mA /厘米^ 2。所描述的自供电，支持物联网的喷墨印刷电致变色器件，在柔性基板上制造，展示了可穿戴电子产品的潜在应用。
{"title":"Self-Powered, Inkjet Printed Electrochromic Films on Flexible and Stretchable Substrate for Wearable Electronics Applications","authors":"E. Azhar, T. Alford, Hongbin Yu","doi":"10.1109/ECTC.2018.00028","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00028","url":null,"abstract":"Electrochromic films have been used as a non-emissive material for display applications. Such materials have already been integrated in antiglare rearview mirrors for passenger vehicles as well as smart windows intended for energy savings for buildings. However, most electrochromic materials are deposited on rigid substrates, which prevent its use in flexible and stretchable electronic applications, where low temperature deposition techniques are desired. Additionally, electrochormics require an external power source to drive the underlying reduction/oxidation reaction. In this work, electrochromic materials inkjet-printed onto flexible and stretchable substrates have been explored. These devices are \"self-powered\" by organic solar cells also fabricated on flexible and stretchable substrate such as PDMS and PET. A set of inks based on a combination of synthesized and commercially obtained WO_3 nanoparticles, W-TiO_2 and TiO_2 nanoparticles were evaluated. The microstructure of the nanoparticles used in this study were examined under scanning electron microscopy for examining nanoparticle morphology, x-ray diffraction for chemical and structural characterization, and dynamic light scattering for particle size determination. Electrochromic layers were then ink-jet printed on flexible and stretchable PDMS substrates, using synthesized Ag nanowires as conductive, yet highly transparent electrodes. The stretchable printed electrochromic devices under various stress conditions and electrochromic performances were evaluated and demonstrated clear switching behavior under external bias, with 7 second coloration time, 8 second bleaching time, and 0.36-0.75 optical modulation at ?=525 nm. Cyclic voltammetry and galvanostatic charge/discharge measurements demonstrated high areal capacitance, with limited stability upon cycled operation. The electrochromic devices were then integrated in an Internet of Things (IoT)-enabled switching configuration, self-powered by PCDTBT:PC_70BM organic photovoltaics. The bulk heterojunction devices were evaluated with varying hole-transport layers and substrates, and exhibited the strongest performance of PCE? 3%, V_oc=0.9V and J_sc ? 10-15 mA/cm^2. The described self-powered, IoT-enabled, ink-jet printed electrochromic devices, fabricated on flexible substrates, are demonstrative of potential applications for wearable electronics.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"31 1","pages":"131-138"},"PeriodicalIF":0.0,"publicationDate":"2018-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80013691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Ishigure, Hikaru Masuda, Kumi Date, Chinami Marushima, Tadayuki Enomoto
In this paper, we represent an innovative technology for integrating optical devices: direct fabrication for polymer optical waveguide in a PMT ferrule, a ferrule for polymer waveguides connected with a mechanically transferable (MT) connector using the Mosquito method.
{"title":"Direct Fabrication for Polymer Optical Waveguide in PMT Ferrule Using the Mosquito Method","authors":"T. Ishigure, Hikaru Masuda, Kumi Date, Chinami Marushima, Tadayuki Enomoto","doi":"10.1109/ECTC.2018.00169","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00169","url":null,"abstract":"In this paper, we represent an innovative technology for integrating optical devices: direct fabrication for polymer optical waveguide in a PMT ferrule, a ferrule for polymer waveguides connected with a mechanically transferable (MT) connector using the Mosquito method.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"47 1","pages":"1103-1108"},"PeriodicalIF":0.0,"publicationDate":"2018-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75055427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hwan-Pil Park, Seongchul Kim, Taeyoung Lee, S. Yoo, Young-Ho Kim, Jae-Yong Park
The effects of nonconductive adhesive (NCA) trapping on the reliability of low-temperature (150°C) thermo-compression (TC)-bonded flip-chip joints were investigated in this study. Both rough and smooth Cu pads were employed to investigate the effects of surface roughness on NCA trapping, with Sn-Ag solder-capped Cu pillar bumps bonded onto the Cu pads via low-temperature TC bonding. The NCA trapping in the rough Cu pad sample was much greater than that in the smooth Cu pad sample after TC bonding. In addition, the NCA trapping increased with decreasing bonding pressure. The electrical resistance for both the rough and smooth Cu pad samples increased after preconditioning (moisture sensitive level 3) and thermal cycling (-55°C/125°C) reliability tests. The high electrical resistance of the rough Cu pad sample was due to the crack propagation caused by the expansion of the trapped NCA. The reliability of the flip chip joint increased with increasing bonding pressure increased and decreasing surface roughness.
{"title":"The Reliability and the Effect of NCA Trapping in Thermo-Compression Flip-Chip Solder Joints Fabricated Using Sn-Ag Solder Capped 40 µm Pitch Cu Pillar Bumps and Low Temperature Curable Non-Conductive Adhesive (NCA)","authors":"Hwan-Pil Park, Seongchul Kim, Taeyoung Lee, S. Yoo, Young-Ho Kim, Jae-Yong Park","doi":"10.1109/ECTC.2018.00290","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00290","url":null,"abstract":"The effects of nonconductive adhesive (NCA) trapping on the reliability of low-temperature (150°C) thermo-compression (TC)-bonded flip-chip joints were investigated in this study. Both rough and smooth Cu pads were employed to investigate the effects of surface roughness on NCA trapping, with Sn-Ag solder-capped Cu pillar bumps bonded onto the Cu pads via low-temperature TC bonding. The NCA trapping in the rough Cu pad sample was much greater than that in the smooth Cu pad sample after TC bonding. In addition, the NCA trapping increased with decreasing bonding pressure. The electrical resistance for both the rough and smooth Cu pad samples increased after preconditioning (moisture sensitive level 3) and thermal cycling (-55°C/125°C) reliability tests. The high electrical resistance of the rough Cu pad sample was due to the crack propagation caused by the expansion of the trapped NCA. The reliability of the flip chip joint increased with increasing bonding pressure increased and decreasing surface roughness.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"1937-1941"},"PeriodicalIF":0.0,"publicationDate":"2018-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78631651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chenhui Li, R. Stabile, F. Kraemer, Teng Li, O. Raz
In this paper, based on a wet etched silicon interposer, we propose a 2.5D assembly of two dimensional optical transceivers for 400 Gbps parallel optical interconnections. In this opto-electronic packaging, two dimensional optical matrix is formed as 250 µm in both the x -and y-directions by exploiting commercial opto-electronic arrays, and a compact optical interface is used to couple the light channels with fiber ribbons. Each quadrant of the optical matrix is connected with its CMOS IC part via impedance matched co-planner wave guides. The shortest traces between optics and CMOS ICs can be 300 µm, benefiting from flip-chip technology. The process flow of silicon interposer fabrication is illustrated. With flip-chip bonding, 25 Gbps 2D 16-channel receiver is assembled on the silicon interposer, and the sub-module, including the optical interface, is scaled down to 4 mm by 6 mm. In addition, the performance of this assembled module is fully characterized. Uniform and clear eye patterns are captured for all of the channels. Receiver sensitivities are also tested for all channels at 25.78 Gbps, 2 31-1 PRBS, with the variation less than 1.5 dB at error free operation.
{"title":"400 Gbps 2-Dimensional Optical Receiver Assembled on Wet Etched Silicon Interposer","authors":"Chenhui Li, R. Stabile, F. Kraemer, Teng Li, O. Raz","doi":"10.1109/ECTC.2018.00131","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00131","url":null,"abstract":"In this paper, based on a wet etched silicon interposer, we propose a 2.5D assembly of two dimensional optical transceivers for 400 Gbps parallel optical interconnections. In this opto-electronic packaging, two dimensional optical matrix is formed as 250 µm in both the x -and y-directions by exploiting commercial opto-electronic arrays, and a compact optical interface is used to couple the light channels with fiber ribbons. Each quadrant of the optical matrix is connected with its CMOS IC part via impedance matched co-planner wave guides. The shortest traces between optics and CMOS ICs can be 300 µm, benefiting from flip-chip technology. The process flow of silicon interposer fabrication is illustrated. With flip-chip bonding, 25 Gbps 2D 16-channel receiver is assembled on the silicon interposer, and the sub-module, including the optical interface, is scaled down to 4 mm by 6 mm. In addition, the performance of this assembled module is fully characterized. Uniform and clear eye patterns are captured for all of the channels. Receiver sensitivities are also tested for all channels at 25.78 Gbps, 2 31-1 PRBS, with the variation less than 1.5 dB at error free operation.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"140 1","pages":"848-853"},"PeriodicalIF":0.0,"publicationDate":"2018-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86669805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, the four-point bending method experiments were carried out with different polyimides and passivation layers for realization of adhesion property below 400°C. Three types of passivation layers, thermal oxide, tetraethoxysilane (TEOS) oxide, silicon nitride, and three types of polyimides, with hydrophobic silane, with hydrophilic silane and without silane, and annealing temperature were all considered in this paper. Moreover, the relation between adhesion strength and surface roughness is discussed. Finally, a low thermal budget (250-375°C) polyimide/metal hybrid bonding scheme with good stress release was proposed for future hybrid bonding applications.
{"title":"Adhesion Property of Polyimide and Passivation Layer for Polymer/metal Wafer-Level Hybrid Bonding in 3D Integration","authors":"Cheng-Hsien Lu, Y. Kho, Yu-Tao Yang, Yu‐Pei Chen, Chiao-Pei Chen, Tsung-Tai Hung, Chiu-Feng Chen, Kuan-Neng Chen","doi":"10.1109/ECTC.2018.00067","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00067","url":null,"abstract":"In this paper, the four-point bending method experiments were carried out with different polyimides and passivation layers for realization of adhesion property below 400°C. Three types of passivation layers, thermal oxide, tetraethoxysilane (TEOS) oxide, silicon nitride, and three types of polyimides, with hydrophobic silane, with hydrophilic silane and without silane, and annealing temperature were all considered in this paper. Moreover, the relation between adhesion strength and surface roughness is discussed. Finally, a low thermal budget (250-375°C) polyimide/metal hybrid bonding scheme with good stress release was proposed for future hybrid bonding applications.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"22 1","pages":"401-406"},"PeriodicalIF":0.0,"publicationDate":"2018-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86997841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hwan-Pil Park, Young-Ho Kim, Y. Jang, Sung‐Hoon Choa
We investigated die warpage by applying under bump metallurgy (UBM) on die backside metallization for fan-out package process applications. An oxidized silicon wafer was used for the substrate, and an oxide layer was used on the active side of the die. Die warpage was controlled by applying UBM layers on the die backside. The thickness of the copper in the UBM layers was varied to 3 µm, 5 µm, and 7 µm. Two types of polyimide (PI) layers between the UBM layers formed and reduced die warpage, which was measured by the shadow moiré measurement method. Also, the thickness of the electro-plated copper in the UBM layers and the PI layers before the UBM layers affected the degree of die warpage during reflow. When forming the PI layer on the die before the UBM, the degree of die warpage was decreased compared to that without the PI layer in the cooling temperature range of the reflow profile. The silicon dies exhibited no warpage near the solder solidification temperature. This structure and process using a backside UBM layer and molten solder in the flip-chip bonding not only improved die shifts, but controlled die warpage during die pick -and-placement processes for fan-out packaging applications and also controlled die warpage during the die pick -and-placement step and in stack-via height formation process applications.
{"title":"Controlling Die Warpage by Applying Under Bump Metallurgy for Fan-Out Package Process Applications","authors":"Hwan-Pil Park, Young-Ho Kim, Y. Jang, Sung‐Hoon Choa","doi":"10.1109/ECTC.2018.00286","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00286","url":null,"abstract":"We investigated die warpage by applying under bump metallurgy (UBM) on die backside metallization for fan-out package process applications. An oxidized silicon wafer was used for the substrate, and an oxide layer was used on the active side of the die. Die warpage was controlled by applying UBM layers on the die backside. The thickness of the copper in the UBM layers was varied to 3 µm, 5 µm, and 7 µm. Two types of polyimide (PI) layers between the UBM layers formed and reduced die warpage, which was measured by the shadow moiré measurement method. Also, the thickness of the electro-plated copper in the UBM layers and the PI layers before the UBM layers affected the degree of die warpage during reflow. When forming the PI layer on the die before the UBM, the degree of die warpage was decreased compared to that without the PI layer in the cooling temperature range of the reflow profile. The silicon dies exhibited no warpage near the solder solidification temperature. This structure and process using a backside UBM layer and molten solder in the flip-chip bonding not only improved die shifts, but controlled die warpage during die pick -and-placement processes for fan-out packaging applications and also controlled die warpage during the die pick -and-placement step and in stack-via height formation process applications.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"8 1","pages":"1912-1919"},"PeriodicalIF":0.0,"publicationDate":"2018-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73305621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Decreasing dimensions of copper conductor lines in redistribution layers of upcoming fan-out wafer-level packages involve increasing demands in terms of reliability. Due to the different thermal expansion of the different materials of the package, the lines suffer from high mechanical stress. This stress may ultimately lead to failure of the conductor. The corresponding failure mode was found to be transgranular brittle fracture along the grain boundaries of the copper. Literature studies revealed, that sulfur and chloride impurities in the deposit accumulate at the grain boundaries and render them brittle. In addition, impurity-driven accumulation of voids during annealing was found, which further weakens the grain boundaries. Such weakening of the grain boundaries was combined with a literature known transition from plastic to brittle deformation as a function of the ratio of the grain size versus the deposit thickness. As a conclusion, deposits of high purity and large grain size are required to improve the reliability of the thin copper lines. Both parameters may be affected by properly designed plating additives. Guidelines for the design of suitable levelers require in-depth knowledge of the effect of functional groups on the plating process and may be obtained based on spectroscopy and electrochemistry. Impurity analysis of deposits obtained from a plating process based on a leveler, which was synthesized according to the provided guidelines, indeed yielded copper of high purity. Such process is supposed to be well-suitable for upcoming fine-pitch redistribution layer lines.
{"title":"Optimization of Electrodeposited Copper for Sub 5 µm L/S Redistribution Layer Lines by Plating Additives","authors":"Ralf Schmidt, T. Beck, R. Rooney, A. Gewirth","doi":"10.1109/ECTC.2018.00188","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00188","url":null,"abstract":"Decreasing dimensions of copper conductor lines in redistribution layers of upcoming fan-out wafer-level packages involve increasing demands in terms of reliability. Due to the different thermal expansion of the different materials of the package, the lines suffer from high mechanical stress. This stress may ultimately lead to failure of the conductor. The corresponding failure mode was found to be transgranular brittle fracture along the grain boundaries of the copper. Literature studies revealed, that sulfur and chloride impurities in the deposit accumulate at the grain boundaries and render them brittle. In addition, impurity-driven accumulation of voids during annealing was found, which further weakens the grain boundaries. Such weakening of the grain boundaries was combined with a literature known transition from plastic to brittle deformation as a function of the ratio of the grain size versus the deposit thickness. As a conclusion, deposits of high purity and large grain size are required to improve the reliability of the thin copper lines. Both parameters may be affected by properly designed plating additives. Guidelines for the design of suitable levelers require in-depth knowledge of the effect of functional groups on the plating process and may be obtained based on spectroscopy and electrochemistry. Impurity analysis of deposits obtained from a plating process based on a leveler, which was synthesized according to the provided guidelines, indeed yielded copper of high purity. Such process is supposed to be well-suitable for upcoming fine-pitch redistribution layer lines.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":" 79","pages":"1220-1225"},"PeriodicalIF":0.0,"publicationDate":"2018-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91410316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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