Research and Design of Pipeline Register Structure Based on Coarse-grained Reconfigurable Array

Abstract

It is difficult to implement efficient and flexible algorithm mapping because the structure of the pipeline register based on the coarse-grained reconfigurable array is fixed. This paper analyzes the algorithm data flow diagram with a loop structure, and proposes a configurable pipeline register structure. By designing an output configuration selection circuit, a smaller hardware resource is consumed for a greater flexibility. Experimental results show that the configurable coarse-grained reconfigurable array pipeline register structure proposed in this paper can achieve the algorithm mapping performance no less than the fixed pipeline register in the three pipeline modes. Even with a greater difference between the critical path delay of each PE, the proposed structure will performance better.