M. Sakamoto, Shuusaku Mizukami, D. Hamano, H. Fujisaka
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引用次数: 0
Abstract
A novel 4-operand redundant binary adder by using neuron MOS is described. Proposed adder can achieve totally parallel multi-operand addition, because four input operands can be added simultaneously without the carry propagation chain by our novel addition algorithm. The principle of this algorithm is to utilize the partial addition in every two digits block. The neuron MOSFETs are applied to the implementation of this system, accordingly the ternary operations for the redundant binary number and the multi-input operations can be simply realized. The features of the proposed adder are capability of high speed operation and less number of transistors as compared with the conventional binary one. Simulations have been made by HSPICE.
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