A design of 4-operand redundant binary parallel adder using neuron MOS

M. Sakamoto, Shuusaku Mizukami, D. Hamano, H. Fujisaka
{"title":"A design of 4-operand redundant binary parallel adder using neuron MOS","authors":"M. Sakamoto, Shuusaku Mizukami, D. Hamano, H. Fujisaka","doi":"10.1109/ISCAS.2004.1329391","DOIUrl":null,"url":null,"abstract":"A novel 4-operand redundant binary adder by using neuron MOS is described. Proposed adder can achieve totally parallel multi-operand addition, because four input operands can be added simultaneously without the carry propagation chain by our novel addition algorithm. The principle of this algorithm is to utilize the partial addition in every two digits block. The neuron MOSFETs are applied to the implementation of this system, accordingly the ternary operations for the redundant binary number and the multi-input operations can be simply realized. The features of the proposed adder are capability of high speed operation and less number of transistors as compared with the conventional binary one. Simulations have been made by HSPICE.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"42 1","pages":"II-793"},"PeriodicalIF":0.0000,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS.2004.1329391","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

A novel 4-operand redundant binary adder by using neuron MOS is described. Proposed adder can achieve totally parallel multi-operand addition, because four input operands can be added simultaneously without the carry propagation chain by our novel addition algorithm. The principle of this algorithm is to utilize the partial addition in every two digits block. The neuron MOSFETs are applied to the implementation of this system, accordingly the ternary operations for the redundant binary number and the multi-input operations can be simply realized. The features of the proposed adder are capability of high speed operation and less number of transistors as compared with the conventional binary one. Simulations have been made by HSPICE.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
基于神经元MOS的四操作数冗余二进制并行加法器设计
介绍了一种基于神经元MOS的四操作数冗余二进制加法器。所提出的加法器可以实现完全并行的多操作数加法,因为该算法可以同时对四个输入操作数进行加法,而不需要进位传播链。该算法的原理是利用每两位数块的部分加法。该系统采用神经元mosfet实现,可以简单地实现冗余二进制数的三元运算和多输入运算。与传统的二进制加法器相比,该加法器具有运算速度快、晶体管数量少的特点。HSPICE已经进行了模拟。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Accurate fault detection in switched-capacitor filters using structurally allpass building blocks Silicon on sapphire CMOS architectures for interferometric array readout Implementation of Farrow structure based interpolators with subfilters of odd length Dual-edge triggered level converting flip-flops A novel CMOS double-edge triggered flip-flop for low-power applications
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1