Automatic Test Generation Methodology for Verification of a Cache Memory Based on the Graph Model of Cache Hierarchy

Abstract

In modern heterogeneous System-on-Chip (SoC), the cache hierarchy is one of the most complex and problematic components. Due to a huge number of possible cache hierarchy states, verification of the cache hierarchy requires numerous complex tests, which becomes the main problem for functional and formal verification. The most common solution to this problem is to develop specialized test generators for a single level of cache. However, for the entire cache hierarchy, such generators cover only a few localized subsets of the global state space leaving large gaps between these subsets. A verification test generator was developed based on the graph model to cover the entire state space. The proposed approach revealed several critical errors in verifying the VLIW DSP processor hierarchy cache with the Elcore50 architecture. In the future, it is planned to apply this approach to verify other processor cores.