Efficient FPGA Implementation of Novel Cryptographic Hashing Core

Abstract

Hash functions are utilized in the security layer of every communication protocol and in signature authentication schemes for electronic transactions. As time passes more sophisticated applications arise that address to more users-clients and thus demand for higher throughput. Furthermore, due to the tendency of the market to minimize devices size and increase their autonomy to make them portable, power issues should also be taken into consideration. Long rumored and now official, the popular and widely used SHA-1 hashing algorithm has been attacked successfully by researchers in China and the US. It is obvious that sometime in the near future the demand for more secure hash functions will arise but these hash functions should also fulfill industry's expectations as long as the throughput, the area and the power of these new implementations are concerned. In this paper, an implementation of SHA-256 is presented in which the achieved throughput exceeds the limit of 2 Gbps. Furthermore, power dissipation is kept low in such way that the proposed implementation can be characterized as low-power.