{"title":"Low-voltage linear voltage regulator suitable for memories","authors":"W. Aloisi, S.M. Bille, G. Palumbo","doi":"10.1109/ISCAS.2004.1328213","DOIUrl":null,"url":null,"abstract":"In this communication a low-voltage linear voltage regulator in CMOS technology is presented. It is based on a two class-AB gain stage and, hence, does not suffer from internal slew-rate limitation when very large load capacitances are used. The linear regulator suitable for memory application was designed in a 0.35 /spl mu/m standard CMOS technology. The regulator can work with a no-regulated input voltage in the range from 1.3 V to 3 V providing a regulated voltage of 1 V with a load capacitance of 2.2 nF.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"34 1","pages":"I-I"},"PeriodicalIF":0.0000,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS.2004.1328213","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
In this communication a low-voltage linear voltage regulator in CMOS technology is presented. It is based on a two class-AB gain stage and, hence, does not suffer from internal slew-rate limitation when very large load capacitances are used. The linear regulator suitable for memory application was designed in a 0.35 /spl mu/m standard CMOS technology. The regulator can work with a no-regulated input voltage in the range from 1.3 V to 3 V providing a regulated voltage of 1 V with a load capacitance of 2.2 nF.
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