Dynamic Channel Flow Control of Networks-on-Chip Systems for High Buffer Efficiency

Abstract

System-on-Chip (SoC) designs become more complex nowadays. The communication between each processing element often suffers challenges due to the wiring problem. Networks-on-Chip (NoC) provides a practical solution to solve the problem. The major components in NoC are routers, which are dominated by the buffer size. Previous mechanisms need large buffer size to achieve high performance. In this paper, a dynamic channel flow control mechanism is proposed to realize the channel resource sharing globally, which can increase the throughput and the channel utilization rate. An 8 × 8 mesh on-chip network is implemented on a cycle accurate simulator. By the experimental result, the proposed mechanism can reduce the buffer size by 30% as compared with virtual channel flow control at the same throughput. Moreover, the throughput can be improved by 20% as compared with wormhole flow control.