Current-mode algorithmic pipeline analog-to-digital converter

Abstract

Current-mode integrated circuit design techniques offering full compatibility with mainstream digital CMOS technology have been investigated for the realization of an 8-bit 1 MHz analog-to-digital converter. This is based on a modular 1-bit-per-stage pipeline architecture employing a compact algorithmic processing circuitry in each stage. The prototype chip fabricated in a 1.2 /spl mu/m digital CMOS technology occupies 0.655 mm/sup 2/ of silicon area and dissipates 50 mW at 5 V supply.