A 0.6-V power efficient digital LDO with 99.7% current efficiency utilizing load current aware clock modulation for fast transient response

K. G. Jayaraman, Karim Rawy, T. T. Kim
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引用次数: 1

Abstract

This paper describes a fully integrated, low voltage digital low-dropout voltage (DLDO) regulator for ultra-low power applications with a load current aware clock modulation scheme. The proposed DLDO uses a clock modulation technique that provides a fast transient response during load state transitions. The proposed clock modulation (CM) controls the clock frequency when it senses a sudden load current transition. This eliminates the tradeoff between transient time and power efficiency with a fixed clock frequency. Thus, it minimizes the transient response time and maximizes the power and current efficiency. The proposed DLDO operates at 0.6 V and generates 0.55 V output voltage. A test chip is fabricated using 65-nm CMOS technology and demonstrates the current efficiency of 99.7% with the load current from 10 μA to 200 μA with and the quiescent current of 0.9 μA.
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具有99.7%电流效率的0.6 v高效数字LDO,利用负载电流感知时钟调制实现快速瞬态响应
本文介绍了一种完全集成的低压数字低降电压(DLDO)稳压器,用于具有负载电流感知时钟调制方案的超低功耗应用。提出的DLDO使用时钟调制技术,在负载状态转换期间提供快速的瞬态响应。提出的时钟调制(CM)控制时钟频率,当它检测到一个突然负载电流转换。这消除了瞬态时间和功率效率与固定时钟频率之间的权衡。因此,它最大限度地减少了瞬态响应时间,最大限度地提高了功率和电流效率。该DLDO工作电压为0.6 V,输出电压为0.55 V。在负载电流为10 μA ~ 200 μA,静态电流为0.9 μA的情况下,采用65 nm CMOS工艺制作了测试芯片,测试结果表明,电流效率为99.7%。
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