Design of low power magnitude comparator

Abstract

A low power two bit magnitude comparator has been proposed in the present work. The proposed magnitude comparator using the technology of coupling has been compared with the basic comparator circuit. The performance analysis of both the different comparators has been done for power consumption, delay and power delay-product (PDP) with VDD sweep. The simulations are carried on Mentor graphics (ELDO Spice) using 90nm CMOS technology at 1 V supply. The simulation results of the coupled magnitude comparator circuits is in good agreement in terms of power consumption at percentage of 60.26% in greater than function and 56.14% in lesser than f unction and 59.48% in equals to function comparators.